library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity turbo is
port (rst: in STD_LOGIC;
enSYS: in std_logic;
enXDS: in std_logic;
clk40: in STD_LOGIC;
clk48: in STD_LOGIC;
selSYS: in STD_LOGIC_VECTOR (2 downto 0);
selXDS: in STD_LOGIC_VECTOR (2 downto 0);
clkSYS: out STD_LOGIC;
clkCPU: out STD_LOGIC;
clkXDS: out STD_LOGIC);
end turbo;
architecture Behavioral of turbo is
component div2
port (clkin : in STD_LOGIC;
rst : in STD_LOGIC;
clkout : out STD_LOGIC);
end component;
component mod3
port (clkin: in std_logic;
rst: in std_logic;
clkout: out std_logic);
end component;
component mod5
port (clkin: in std_logic;
rst: in std_logic;
clkout: out std_logic);
end component;
component mux8
port (en: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (2 downto 0);
D0,D1,D2,D3,D4,D5,D6,D7: in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal clk24: std_logic;
signal clk20: std_logic;
signal clk16: std_logic;
signal clk13: std_logic;
signal clk12: std_logic;
signal clk10: std_logic;
signal clk9: std_logic;
signal clk8: std_logic;
signal clk4: std_logic;
signal clkS: std_logic;
begin
C24: div2 port map (clk48,rst,clk24);
C20: div2 port map (clk40,rst,clk20);
C16: mod3 port map (clk48,rst,clk16);
C13: mod3 port map (clk40,rst,clk13);
C12: div2 port map (clk24,rst,clk12);
C10: div2 port map (clk20,rst,clk10);
C9: mod5 port map (clk48,rst,clk9);
C8: div2 port map (clk16,rst,clk8);
C4: div2 port map (clk8,rst,clk4);
MST: mux8 port map (enSYS,selSYS,clk8,clk12,clk16,clk20,'0','0','0',clk4,clkS);
MSYS: clkSYS <= clkS;
MCPU: div2 port map (clkS,rst,clkCPU);
MXDS: mux8 port map (enXDS,selXDS,clk8,clk9,clk10,clk12,clk13,clk16,'0','0',clkXDS);
end Behavioral;
