Awesome !!!

it does not synthesize. Even with latest MiST modules
it takes more than 20 minutes, I have stopped , isn't it too much ?
Using Q13.

Regards

Hey Super GFlorez! ! !

If Kyp has given György access to the Git, let the magic flow.
I don't know if it has anything related with it, but being György Hungarian it would be too strange if György didn't know about Enteprise,  being Hungary one of the countries with the most active users.

Hi!

I noticed this core was not ported to MiST. I would try to do it, but can you open the source? Or just share with me on GitHub (I won't publish it if you don't want, I promise). BTW, I'm sure it's using some of my code, too, like the improved T80.

Hi Gyurco. I would like to thank you very much for your proposal. It was precisely me who told Dr.OG if he could contact you, thinking of all the people who have a MiST, MiSTica or SiDi boards and who constantly ask me if there will be a version for these FPGAs.

The main problem that we detect is that the BRAM is insufficient, since 64K are necessary for VRAM and that it is accessed by the Z80 and by the NICK. The firmware and the core do not fit at the same time. So almost all the BRAM is used by the Enter and there is nothing left for the firmware it needs, at least 8K.

I couldn't tell you much more, maybe Kyp has more ideas. If Nick accesses 14MHz, I don't think SDRAM supports it and I don't think waiting states can be added to the video. It is possible that reading in burst mode is possible, but it escapes us. In the enter, video and cpu use independent clocks and without any relationship between them.

Anyway thanks a lot for your help !!!

Here:
http://retrowiki.es/viewtopic.php?f=107&t=200037978&p=200154151#p200154146

and here:
https://misterfpga.org/viewtopic.php?t=4645

https://www.twitch.tv/retrocrypta
22:00 CET

Hello. Those of you who have a MiSTer or a NeptUNO board can now try the core.



And for those who have a MiST or a SIDi, as soon as the core is finished testing, debugging and sources are released, you'll need to talk to SlingShot (Gyurco) ( György Szombathelyi ) about making a MiST fpga port. Dr.OG knows from Atari-Forum.

Currently the core does not work on MiST / SiDi because the lack of BRAM. These fpga boards only have 70KB of BRAM and it is insufficient for the framework and VRAM, which would have to go in SDRAM.

He has made much more complex ports. Would be a way to make this core work on MiST.

FeedBack testing the core is really appreciated.

Cheers !