Look at the pinouts

Damn, I should have thought of that!

Are you going to build memory expansion for the spare machine?

So this is how I understand the memory expansion works:

MREQ is used to trigger the RAS / CAS delay capacitors to the address multiplexers when A16 is high and A17-21 are low and /RD or /WR are low. This feeds the address to the 4164 chips with suitable RAS / CAS delays. Quite neat.

So a read or write in the memory range of 0x1xxxx will access the internal memory expansion.

For a modern SRAM based memory expansion you'd just need to decode A16-A21 as you like for the SRAM size (from 0x10000 up), then enable the SRAM when MREQ is low and read or write are low.

I'm not that familiar wit the Z80, so if you could sanity check for me Zozo? 

Ok, that makes sense. How does the memory mapping work from A0-A21 to segment numbers?

The internal 64K RAM expansion seems to decode A21-A16 = 000001b, or 0x1nnnn. Ah, I have that inverted because it's an active low input, so it should be 111110b? Which would be segment F8, which makes more sense...

So if I wanted to map 512K SRAM to an internal memory expansion which would include segments F8-FB, could I use A21-A19 = 111b and just waste 64KB of the SRAM without causing any problems?

Edit: Hmm, it looks like the /ACCESS line of the Nick drives the data bus on VRAM access. So I would need to ensure the internal RAM expansion does not drive the data bus in segments FC-FF?

With some more ICs can do the trick to decode for DC to FB.

I'll have a think about that!

If you can safely drive the bus with FC-FF being a mirror, then that's a really simple address decoder. I'll see how easy a PAL would be to decode the address properly...

If you are interested I have a spare official enterprise 64K expansion board.  
I was going to upgrade my EP64 but I decided to buy an EP128 instead!

Russ

No rpoblem.

That sounds good, £10!  I might be interested in something like that to upgrade my EP128!