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Author Topic: Enterprise MIDI hardware (Read 1050 times)

Offline Tutus

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Enterprise MIDI hardware
« on: 2018.December.12. 10:00:42 »
An idea came (The idea of ​​Szipucsu and Tutus). Somehow, you should have Midi hardware on your Enterprise computer.
We currently see that Zozo has an old "A" studio copy (see the picture - does not work...).
Pear would take the project in his hands :)

« Last Edit: 2018.December.12. 10:12:42 by szipucsu »

Offline szipucsu

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Re: Enterprise MIDI hardware
« Reply #1 on: 2018.December.12. 10:19:02 »
Yes, but Pear would need some help, as I know.
SOUND SOURCE 3,STYLE 16,LEFT 16,RIGHT 64,SYNC 2
SOUND SOURCE 2,STYLE 128,PITCH 25.2,SYNC 2
SOUND PITCH 25,SYNC 2
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Offline Zozosoft

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Re: Enterprise MIDI hardware
« Reply #2 on: 2018.December.12. 10:50:47 »
see the picture - does not work...
This is at Werner's, this works.
« Last Edit: 2018.December.17. 20:16:44 by szipucsu »

Online gflorez

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Re: Enterprise MIDI hardware
« Reply #3 on: 2018.December.12. 11:55:35 »
There is an old thread about the Scoretrack program.

I would love to have one of these MIDI interfaces, but the cartridge bay is better populated with a good SD-reader. Maybe it would be more realistic to build an external board, for example cloning the Philips NMS-1205 MSX cartridge MIDI side. This is the actual link to the Service Manual

22377-0

Once the interface working, any of our resident genius coders can take the Scoretrack incomplete Rom and make it work.

Edit: I have somehow made the NMS-1205 cartridge work on the Enterprise with the M-Slot adapter.
« Last Edit: 2018.December.12. 12:04:27 by gflorez »

Offline Zozosoft

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Re: Enterprise MIDI hardware
« Reply #4 on: 2018.December.12. 12:11:41 »
I would love to have one of these MIDI interfaces, but the cartridge bay is better populated with a good SD-reader.
Easy to adapt to bus side, just need to add 64K memory address decoder (two 74LS138 can do the task).

Online gflorez

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Re: Enterprise MIDI hardware
« Reply #5 on: 2018.December.12. 12:34:14 »
You mean an external MIDI interface+ROM?

Offline Zozosoft

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Re: Enterprise MIDI hardware
« Reply #6 on: 2018.December.12. 12:49:19 »
You mean an external MIDI interface+ROM?
Yes, the original 'a' Studio interface can be built to expansion port, just need to make a CART signal (address decoding for a 64K).

(Also possible to build cartridge to bus adapter board, for connect any cartridge to expansion bus.)

Online gflorez

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Re: Enterprise MIDI hardware
« Reply #7 on: 2018.December.12. 14:36:51 »
Interesting....

Offline IstvanV

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Re: Enterprise MIDI hardware
« Reply #8 on: 2018.December.12. 15:20:26 »
Is the hardware to be designed for input (modified version of midiplay), or only output from Scoretrack?

Offline Tutus

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Re: Enterprise MIDI hardware
« Reply #9 on: 2018.December.12. 16:26:27 »
Be sure to plan for input. (of course midiplay is compatible).
For external midi keyboard.

Offline Zozosoft

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Re: Enterprise MIDI hardware
« Reply #10 on: 2018.December.12. 16:31:56 »
I'm interested about the output :-) Want to hear in a real life the musics what we found in one Paradise Software tape.

Offline IstvanV

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Re: Enterprise MIDI hardware
« Reply #11 on: 2018.December.12. 17:14:26 »
Be sure to plan for input. (of course midiplay is compatible).
For external midi keyboard.

Midiplay would probably need modifications, the MIDI interface in ep128emu is not based on the cartridge, and is easy to use in EP software with buffered (255 bytes FIFO) and filtered MIDI data. But simple serial port hardware does not have those features, it just gives the raw MIDI input and buffers 1 byte. Hopefully the cartridge can generate an IRQ whenever a byte is received.

Online pear

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Re: Enterprise MIDI hardware
« Reply #12 on: 2018.December.12. 18:36:28 »
I have at least a controller for a good start :) I wonder if it works ?
Code: VHDL
  1. --===========================================================================--
  2. --
  3. --  S Y N T H E Z I A B L E    ACIA 6850   C O R E
  4. --
  5. --  www.OpenCores.Org - January 2007
  6. --  This core adheres to the GNU public license
  7. --
  8. -- Design units   : 6850 ACIA core
  9. --
  10. -- File name      : ACIA6850.vhd
  11. --
  12. -- Purpose        : Implements an RS232 Asynchronous serial communications device
  13. --
  14. -- Dependencies   : ieee.std_logic_1164
  15. --                  ieee.numeric_std
  16. --                  unisim.vcomponents
  17. --
  18. --===========================================================================--
  19. -------------------------------------------------------------------------------
  20. -- Revision list
  21. -- Version   Author                 Date           Changes
  22. --
  23. -- 0.1      Ovidiu Lupas     15 January 2000       New model
  24. -- 1.0      Ovidiu Lupas     January  2000         Synthesis optimizations
  25. -- 2.0      Ovidiu Lupas     April    2000         Bugs removed - RSBusCtrl
  26. --          the RSBusCtrl did not process all possible situations
  27. --
  28. --        olupas at the domain opencores.org
  29. --
  30. -- 3.0      John Kent        October  2002         Changed Status bits to match mc6805
  31. --                                                 Added CTS, RTS, Baud rate control
  32. --                                                 & Software Reset
  33. -- 3.1      John Kent        5 January 2003        Added Word Format control a'la mc6850
  34. -- 3.2      John Kent        19 July 2003          Latched Data input to UART
  35. -- 3.3      John Kent        16 January 2004       Integrated clkunit in rxunit & txunit
  36. --                                                 Now has external TX 7 RX Baud Clock
  37. --                                                 inputs like the MC6850...
  38. --                                                 also supports x1 clock and DCD.
  39. -- 3.4          John Kent                       13 September 2005               Removed LoadCS signal.
  40. --                                                                                                                                      Fixed ReadCS and Read in "if" in
  41. --                                                                                                                                      miniuart_DCD_Init process
  42. -- 3.5      John Kent         28 November 2006     Cleaned up code.
  43. --
  44. -- 4.0      John Kent         3 February 2007      renamed ACIA6850
  45. -- 4.1      John Kent         6 February 2007      Made software reset synchronous
  46. --      4.2      John Kent         25 February 2007     Changed sensitivity lists
  47. --                                                 Rearranged Reset process.
  48. --        dilbert57 at the domain opencores.org
  49. --
  50. library ieee;
  51.    use ieee.std_logic_1164.all;
  52.    use ieee.numeric_std.all;
  53. --library unisim;
  54. --      use unisim.vcomponents.all;
  55.  
  56. -----------------------------------------------------------------------
  57. -- Entity for ACIA_6850                                              --
  58. -----------------------------------------------------------------------
  59.  
  60. --* @brief 6850 ACIA core
  61. --*
  62. --* Syntheziable    ACIA 6850   core.
  63. --*
  64. --* @author Ovidiu Lupas
  65. --* @author John Kent
  66. --* @version 4.2 from 25 February 2007
  67.  
  68. entity ACIA_6850 is
  69.   port (
  70.      --
  71.           -- CPU signals
  72.           --
  73.      clk      : in  Std_Logic;  -- System Clock
  74.      rst      : in  Std_Logic;  -- Reset input (active high)
  75.      cs       : in  Std_Logic;  -- miniUART Chip Select
  76.      rw       : in  Std_Logic;  -- Read / Not Write
  77.      irq      : out Std_Logic;  -- Interrupt
  78.      Addr     : in  Std_Logic;  -- Register Select
  79.      DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In
  80.      DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
  81.      --
  82.           -- Uart Signals
  83.           --
  84.      RxC      : in  Std_Logic;  -- Receive Baud Clock
  85.      TxC      : in  Std_Logic;  -- Transmit Baud Clock
  86.      RxD      : in  Std_Logic;  -- Receive Data
  87.      TxD      : out Std_Logic;  -- Transmit Data
  88.           DCD_n    : in  Std_Logic;  -- Data Carrier Detect
  89.      CTS_n    : in  Std_Logic;  -- Clear To Send
  90.      RTS_n    : out Std_Logic );  -- Request To send
  91. end ACIA_6850; --================== End of entity ==============================--
  92.  
  93. --* @brief Architecture for ACIA_6850 Interface registers
  94. --*
  95. --* Implements an RS232 Asynchronous serial communications device
  96. --*
  97. --* @author Ovidiu Lupas
  98. --* @author John Kent
  99. --* @version 4.2 from 25 February 2007
  100.  
  101. architecture rtl of ACIA_6850 is
  102.  
  103.   type DCD_State_Type is ( DCD_State_Idle, DCD_State_Int, DCD_State_Reset );
  104.  
  105.   -----------------------------------------------------------------------------
  106.   -- Signals
  107.   -----------------------------------------------------------------------------
  108.  
  109.   ----------------------------------------------------------------------
  110.   --  Status Register: StatReg
  111.   ----------------------------------------------------------------------
  112.   --
  113.   -- IO address + 0 Read
  114.   --
  115.   -----------+--------+-------+--------+--------+--------+--------+--------+
  116.   --  Irq    | PErr   | OErr  | FErr   |  CTS   |  DCD   |  TxBE  |  RxDR  |
  117.   -----------+--------+-------+--------+--------+--------+--------+--------+
  118.   -- Irq  - Bit[7] - Interrupt request
  119.   -- PErr - Bit[6] - Receive Parity error (parity bit does not match)
  120.   -- OErr - Bit[5] - Receive Overrun error (new character received before last read)
  121.   -- FErr - Bit[4] - Receive Framing Error (bad stop bit)
  122.   -- CTS  - Bit[3] - Clear To Send level
  123.   -- DCD  - Bit[2] - Data Carrier Detect (lost modem carrier)
  124.   -- TxBE - Bit[1] - Transmit Buffer Empty (ready to accept next transmit character)
  125.   -- RxDR - Bit[0] - Receive Data Ready (character received)
  126.   --
  127.   signal StatReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- status register
  128.  
  129.   ----------------------------------------------------------------------
  130.   --  Control Register: CtrlReg
  131.   ----------------------------------------------------------------------
  132.   --
  133.   -- IO address + 0 Write
  134.   --
  135.   -----------+--------+--------+--------+--------+--------+--------+--------+
  136.   --  RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
  137.   -----------+--------+--------+--------+--------+--------+--------+--------+
  138.   -- RxIEnb - Bit[7]
  139.   -- 0       - Rx Interrupt disabled
  140.   -- 1       - Rx Interrupt enabled
  141.   -- TxCtl - Bits[6..5]
  142.   -- 0 1     - Tx Interrupt Enable
  143.   -- 1 0     - RTS high
  144.   -- WdFmt - Bits[4..2]
  145.   -- 0 0 0   - 7 data, even parity, 2 stop
  146.   -- 0 0 1   - 7 data, odd  parity, 2 stop
  147.   -- 0 1 0   - 7 data, even parity, 1 stop
  148.   -- 0 1 1   - 7 data, odd  parity, 1 stop
  149.   -- 1 0 0   - 8 data, no   parity, 2 stop
  150.   -- 1 0 1   - 8 data, no   parity, 1 stop
  151.   -- 1 1 0   - 8 data, even parity, 1 stop
  152.   -- 1 1 1   - 8 data, odd  parity, 1 stop
  153.   -- BdCtl - Bits[1..0]
  154.   -- 0 0     - Baud Clk divide by 1
  155.   -- 0 1     - Baud Clk divide by 16
  156.   -- 1 0     - Baud Clk divide by 64
  157.   -- 1 1     - reset
  158.   signal CtrlReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- control register
  159.  
  160.   ----------------------------------------------------------------------
  161.   -- Receive Register
  162.   ----------------------------------------------------------------------
  163.   --
  164.   -- IO address + 1     Read
  165.   --
  166.   signal RecvReg : Std_Logic_Vector(7 downto 0) := (others => '0');
  167.   ----------------------------------------------------------------------
  168.   -- Transmit Register
  169.   ----------------------------------------------------------------------
  170.   --
  171.   -- IO address + 1     Write
  172.   --
  173.   signal TranReg : Std_Logic_Vector(7 downto 0) := (others => '0');
  174.  
  175.   signal Reset    : Std_Logic;  -- Reset (Software & Hardware)
  176.   signal RxRst    : Std_Logic;  -- Receive Reset (Software & Hardware)
  177.   signal TxRst    : Std_Logic;  -- Transmit Reset (Software & Hardware)
  178.   signal TxDbit   : Std_Logic;  -- Transmit data bit
  179.   signal RxDR     : Std_Logic := '0';  -- Receive Data ready
  180.   signal TxBE     : Std_Logic := '0';  -- Transmit buffer empty
  181.  
  182.   signal FErr     : Std_Logic := '0';  -- Frame error
  183.   signal OErr     : Std_Logic := '0';  -- Output error
  184.   signal PErr     : Std_Logic := '0';  -- Parity Error
  185.  
  186.   signal TxIEnb   : Std_Logic := '0';  -- Transmit interrupt enable
  187.   signal RxIEnb   : Std_Logic := '0';  -- Receive interrupt enable
  188.  
  189.   signal ReadRR   : Std_Logic := '0';  -- Read receive buffer
  190.   signal WriteTR  : Std_Logic := '0';  -- Write transmit buffer
  191.   signal ReadSR   : Std_Logic := '0';  -- Read Status register
  192.  
  193.   signal DCDState : DCD_State_Type;    -- DCD Reset state sequencer
  194.   signal DCDDel   : Std_Logic := '0';  -- Delayed DCD_n
  195.   signal DCDEdge  : Std_Logic := '0';  -- Rising DCD_N Edge Pulse
  196.   signal DCDInt   : Std_Logic := '0';  -- DCD Interrupt
  197.  
  198.   --* ACIA Receiver
  199.   component ACIA_RX
  200.   port (
  201.      Clk     : in  Std_Logic;                    -- Bus Clock signal
  202.      RxRst   : in  Std_Logic;                    -- Reset input
  203.      RxRd    : in  Std_Logic;                    -- Read data strobe
  204.      WdFmt   : in  Std_Logic_Vector(2 downto 0); -- word format
  205.      BdFmt   : in  Std_Logic_Vector(1 downto 0); -- baud format
  206.      RxClk   : in  Std_Logic;                    -- Receive clock input
  207.      RxDat   : in  Std_Logic;                    -- Receive data bit input
  208.      RxFErr  : out Std_Logic;                    -- Framing Error Status signal
  209.      RxOErr  : out Std_Logic;                    -- Overrun Error Status signal
  210.           RxPErr  : out Std_logic;                    -- Parity Error Status signal
  211.      RxRdy   : out Std_Logic;                    -- Data Ready Status signal
  212.      RxDout  : out Std_Logic_Vector(7 downto 0));-- Receive data bus output
  213.   end component;
  214.  
  215.   --* ACIA Transmitter
  216.   component ACIA_TX
  217.   port (
  218.      Clk    : in  Std_Logic;                    -- Bus Clock signal
  219.      TxRst  : in  Std_Logic;                    -- Reset input
  220.      TxWr   : in  Std_Logic;                    -- Load transmit data strobe
  221.      TxDin  : in  Std_Logic_Vector(7 downto 0); -- Transmit data bus input
  222.      WdFmt  : in  Std_Logic_Vector(2 downto 0); -- Word format Control signal
  223.      BdFmt  : in  Std_Logic_Vector(1 downto 0); -- Baud format Control signal
  224.      TxClk  : in  Std_Logic;                    -- Transmit clock input
  225.      TxDat  : out Std_Logic;                    -- Transmit data bit output
  226.      TxEmp  : out Std_Logic );                  -- Tx buffer empty status signal
  227.   end component;
  228.  
  229. begin
  230.   --* Instantiation of internal components
  231.   --*
  232.   RxDev   : ACIA_RX  port map (
  233.                 Clk      => clk,
  234.                                          RxRst    => RxRst,
  235.                                          RxRd     => ReadRR,
  236.                                          WdFmt    => CtrlReg(4 downto 2),
  237.                                          BdFmt    => CtrlReg(1 downto 0),
  238.                                          RxClk    => RxC,
  239.                                          RxDat    => RxD,
  240.                                          RxFErr   => FErr,
  241.                                          RxOErr   => OErr,
  242.                                          RxPErr   => PErr,
  243.                                          RxRdy    => RxDR,
  244.                                          RxDout   => RecvReg
  245.                                          );
  246.  
  247.  
  248.   TxDev   : ACIA_TX  port map (
  249.                 Clk      => clk,
  250.                                          TxRst    => TxRst,
  251.                                          TxWr     => WriteTR,
  252.                                          TxDin    => TranReg,
  253.                                          WdFmt    => CtrlReg(4 downto 2),
  254.                                          BdFmt    => CtrlReg(1 downto 0),
  255.                                          TxClk    => TxC,
  256.                                          TxDat    => TxDbit,
  257.                                          TxEmp    => TxBE
  258.                                          );
  259.  
  260. --* ACIA Reset may be hardware or software
  261. ACIA_Reset : process( clk, rst, Reset, DCD_n )
  262. begin
  263.     -- Asynchronous External reset
  264.     if rst = '1' then
  265.            Reset <= '1';
  266.     elsif clk'Event and clk = '0' then
  267.            -- Synchronous Software reset
  268.            Reset <= CtrlReg(1) and CtrlReg(0);
  269.          end if;
  270.          -- Transmitter reset
  271.          TxRst <= Reset;
  272.          -- Receiver reset
  273.          RxRst <= Reset or DCD_n;
  274.  
  275. end process;
  276.  
  277. --* ACIA Status Register
  278. --* ACIA_Status : process(clk,  Reset, TxIEnb, RxIEnb,
  279. --* RxDR, TxBE,  DCD_n, CTS_n, DCDInt,
  280. --* FErr, OErr,  PErr )
  281. ACIA_Status : process(Reset, clk )
  282.   begin
  283.     if Reset = '1' then
  284.        StatReg <= (others => '0');
  285.     elsif clk'event and clk='0' then
  286.                  StatReg(0) <= RxDR;   -- Receive Data Ready
  287.        StatReg(1) <= TxBE and (not CTS_n); -- Transmit Buffer Empty
  288.             StatReg(2) <= DCDInt; -- Data Carrier Detect
  289.                  StatReg(3) <= CTS_n;  -- Clear To Send
  290.        StatReg(4) <= FErr;   -- Framing error
  291.        StatReg(5) <= OErr;   -- Overrun error
  292.        StatReg(6) <= PErr;   -- Parity error
  293.                  StatReg(7) <= (RxIEnb and RxDR)   or
  294.                                (RxIEnb and DCDInt) or
  295.                                (TxIEnb and TxBE);
  296.     end if;
  297.   end process;
  298.  
  299.  
  300. --* ACIA Transmit Control
  301. --*
  302. ACIA_Control : process( CtrlReg, TxDbit )
  303. begin
  304.     case CtrlReg(6 downto 5) is
  305.          when "00" => -- Disable TX Interrupts, Assert RTS
  306.            RTS_n  <= '0';
  307.                 TxD    <= TxDbit;
  308.                 TxIEnb <= '0';
  309.     when "01" => -- Enable TX interrupts, Assert RTS
  310.            RTS_n  <= '0';
  311.                 TxD    <= TxDbit;
  312.                 TxIEnb <= '1';
  313.     when "10" => -- Disable Tx Interrupts, Clear RTS
  314.            RTS_n  <= '1';
  315.                 TxD    <= TxDbit;
  316.                 TxIEnb <= '0';
  317.     when "11" => -- Disable Tx interrupts, Assert RTS, send break
  318.            RTS_n  <= '0';
  319.                 TxD    <= '0';
  320.                 TxIEnb <= '0';
  321.     when others =>
  322.            null;
  323.          end case;
  324.  
  325.          RxIEnb <= CtrlReg(7);
  326.  
  327. end process;
  328.  
  329. --* Generate Read / Write strobes.
  330. --*
  331. --* ACIA_Read_Write:  process(clk, Reset, cs, rw, Addr, DataIn )
  332. ACIA_Read_Write:  process(clk, Reset )
  333. begin
  334.   if reset = '1' then
  335.             CtrlReg <= (others => '0');
  336.                  TranReg <= (others => '0');
  337.                  ReadRR  <= '0';
  338.                  WriteTR <= '0';
  339.                  ReadSR <= '0';
  340.         elsif clk'event and clk='0' then
  341.        ReadRR  <= '0';
  342.        WriteTR <= '0';
  343.        ReadSR  <= '0';
  344.             if cs = '1' then
  345.               if Addr = '0' then        -- Control / Status register
  346.                      if rw = '0' then   -- write control register
  347.                             CtrlReg <= DataIn;
  348.                           else               -- read status register
  349.                             ReadSR      <= '1';
  350.                           end if;
  351.               else                                         -- Data Register
  352.                      if rw = '0' then   -- write transmiter register
  353.              TranReg <= DataIn;
  354.                   WriteTR <= '1';
  355.                 else               -- read receiver register
  356.              ReadRR  <= '1';
  357.                           end if; -- rw
  358.                    end if; -- Addr
  359.             end if;  -- cs
  360.    end if; -- clk / reset
  361. end process;
  362.  
  363. --* Set Data Output Multiplexer
  364. --*
  365. ACIA_Data_Mux: process(Addr, StatReg, RecvReg)
  366. begin
  367.          if Addr = '1' then
  368.                  DataOut <= RecvReg;   -- read receiver register
  369.          else
  370.                  DataOut <= StatReg;   -- read status register
  371.          end if; -- Addr
  372.     irq <= StatReg(7);
  373. end process;
  374.  
  375.  
  376. --* Data Carrier Detect Edge rising edge detect
  377. --* ACIA_DCD_edge : process( reset, clk, DCD_n, DCDDel  )
  378. ACIA_DCD_edge : process( reset, clk     )
  379. begin
  380.    if reset = '1' then
  381.            DCDEdge <= '0';
  382.                 DCDDel  <= '0';
  383.    elsif clk'event and clk = '0' then
  384.            DCDDel <= DCD_n;
  385.                 DCDEdge <= DCD_n and (not DCDDel);
  386.    end if;
  387. end process;
  388.  
  389.  
  390. --* Data Carrier Detect Interrupt
  391. --* If Data Carrier is lost, an interrupt is generated
  392. --* To clear the interrupt, first read the status register
  393. --* then read the data receive register
  394. --* ACIA_DCD_Int : process( reset, clk, DCDState, DCDEdge, ReadRR, ReadSR )
  395. ACIA_DCD_Int : process( reset, clk )
  396. begin
  397.    if reset = '1' then
  398.            DCDInt   <= '0';
  399.                 DCDState <= DCD_State_Idle;
  400.    elsif clk'event and clk = '0' then
  401.            case DCDState is
  402.                 when DCD_State_Idle =>
  403.                    -- DCD Edge activates interrupt
  404.                    if DCDEdge = '1' then
  405.                       DCDInt     <= '1';
  406.                            DCDState   <= DCD_State_Int;
  407.                    end if;
  408.            when DCD_State_Int =>
  409.                    -- To reset DCD interrupt,
  410.                         -- First read status
  411.                    if ReadSR = '1' then
  412.                            DCDState <= DCD_State_Reset;
  413.                    end if;
  414.                 when DCD_State_Reset =>
  415.                    -- Then read receive register
  416.                    if ReadRR = '1' then
  417.                                 DCDInt   <= '0';
  418.                                 DCDState <= DCD_State_Idle;
  419.          end if;
  420.       when others =>
  421.          null;
  422.       end case;
  423.    end if; -- clk / reset
  424. end process;
  425.  
  426. end rtl; --===================== End of architecture =======================--
  427.  

Online gflorez

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Re: Enterprise MIDI hardware
« Reply #13 on: 2018.December.12. 19:06:49 »
Both the Enterprise MIDI cartridge and the Philips NMS-1205 use the same chip, the Motorola MC68B50P.

Offline Zozosoft

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    • http://enterprise.iko.hu/
Re: Enterprise MIDI hardware
« Reply #14 on: 2018.December.12. 23:10:05 »
Both the Enterprise MIDI cartridge and the Philips NMS-1205 use the same chip, the Motorola MC68B50P.
Atari ST also uses it. (It is the origin of the Enterprise MIDI, because Kopácsy also worked on Atari.)
« Last Edit: 2018.December.17. 20:23:20 by szipucsu »