Yes, you're right. And so it was in the first version.
But I decided to protect themselves in case the LS145 decoder inside the EP was damaged.
Therefore, additional signals KB0 .. KB9 defined on the basis of all the line KB.
Hmm, maybe I dumb, but I still don't understand this clearly.
KB : in STD_LOGIC_VECTOR (9 downto 0);
So you have the KB stuff here. Then lines like this:
signal KB0 : STD_LOGIC;
...
with KB select
KB0 <= '0' when "1111111110",
'1' when others;
Actually "copy" the exact signals from KB logic vector to KB0 ... KB9, so in my opinion eg using KB5 or KB(5) is about the same (well not the very same, since it has some short time of propagation delay, as far as I can guess). I thought the difference can be, if you want to implement a demultiplexer in VHDL that is the KB logic vector is "4 line wide" only and you create your internally used signals from 0 ... 9. But what you do here seems not to be this, but an exact (in my opinion unneeded) copy from KB(9 downto 0) to KB9...KB0 actually.
This is a simple combinatorial logic. Hazards are unlikely.
What I meant (but again, I can be wrong easily, my comments here are more about me to learn VHDL hehe) with a simplified example:
Actually, as far as I know this may not work at all. At least not in a way one would expect. Because with a programming language background some can expect that KB5 has been assigned with a value of logic level 1, then assign KB_J with KB5 which should be '1' then, since the first line was earlier (in the meaning of "sequence" in a programming language). But actually this does not mean anything in VHDL, as the two lines are "executed" in parallel, thus you can't be sure the second line will "see" the already set up value of KB5 or the original, from the point of view of VHDL you can even exchange the two lines above and it will mean still the same. Again, that is _my_ idea about VHDL. So about "hazard" I mean about the situation that you set KB5 and signals with the similar names and you use them then, but the order of "logic evaluation" can be wrong here. You may even see the previous state of the signal instead of what you have expected, as KB5 is not "filled" with the value from the KB std logic vector yet when it's used. What I would do is to put a "process" block to "sense" level change of KB5 and similar signals for the J,K etc process. I am not sure if it's even understandable at all, what I want to say
Yes, operations are performed by hardware in parallel (with an accuracy of the propagation time of signals).
Timing Report shows propagation of signals with differences of 1 ns.
I see, I have not experience at all with this, that's true, since I "know" a very little VHDL just by learning and without actually trying/using it
Since the lack of any hardware I can program (FPGA what I would like to play with, not so much a CPLD, but that's another question).
Well, I can't stop repeating that it's more like a "me trying to understand VHDL" and not a critical view on your work, please do not misunderstand me. I would like to understand this only, but if it looks like off-topic or annoying for you, then I shut up
Thanks!