Author Topic: Enterprise VHDL (Read 11335 times)

Saint · « **Reply #15 on:** 2012.October.09. 10:46:59 »

That's very interesting!

I really need to get a logic analyser so I can see what all the signals are doing when the Z80 clock gets delayed.

Seeing what M1, MREQ, RAS and VCAS are doing while running nops in VRAM would be very useful.

Saint · « **Reply #16 on:** 2012.October.09. 11:01:17 »

A little update on the progress -- I have synthesized a chip which reads in the line parameter blocks, sets the RGB from the palette in pixel mode (only pixel mode done currently) and generates sync.

Currently though I've not been able to get a picture on my VGA monitor (the vertical sync being part of the LPT is a pain for VGA) and debugging sync signals on modern digital TV's is a nightmare. So I'm just building up a cable to connect the DE1 to an old CRT I have in the attic, then I can see what's going on!

James

Saint · « **Reply #17 on:** 2012.October.09. 14:05:49 »

The vertical deflection circuit on my old monitor is dead.

Just one scanline in the middle of the screen.

Damn it.

Zozosoft · « **Reply #18 on:** 2012.October.09. 14:11:30 »

It is bad news

Author Topic: Enterprise VHDL (Read 11335 times)

Saint

Re: Enterprise VHDL

Saint

Re: Enterprise VHDL

Saint

Re: Enterprise VHDL

Zozosoft

Re: Enterprise VHDL