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Author Topic: Enterprise VHDL (Read 11006 times)

Offline Saint

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Enterprise VHDL
« on: 2012.September.19. 10:50:29 »
After thinking about hardware sprites and FPGA's, I came to thinking about an Enterprise in an FPGA. I know this has been talked about to some degree on the forum before.

I've always been interested in FPGA / VHDL development, and have played with the Amiga and ST recreations on the Altera DE1. The most I have done in terms of original work is a very simple sprite engine in VHDL, though.

You have the mainstream components you need for an Enterprise already available, such as Z80 and WD177x, but you'd obviously have to recreate Nick and Dave.

Does anyone here have any more experience of FPGA development?

James

Offline Saint

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Re: Enterprise VHDL
« Reply #1 on: 2012.September.19. 11:17:42 »
This is how the Suska Atari ST FPGA was created --

http://experiment-s.de/en/pictures/english/atari-custom-chips

Recreating each custom chip in turn and testing it on the actual hardware.

It looks like each chip was replaced with a Sphinx C100 FPGA module

http://download.inventronik.de/Sphinx-C100/Sphinx-C100-Docu-en.pdf

Soldered directly onto the motherboard.
« Last Edit: 2012.September.19. 11:29:49 by Saint »

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #2 on: 2012.September.19. 11:52:15 »
Recreating each custom chip in turn and testing it on the actual hardware.
Great idea!
Enterprise is more simple, only 2 custom chips  :ds_icon_cheesygrin:

Anyway it is also possible to made for the first step a "Nick v2.0" as external hw, works as mirror of the original, and later add some enhacements, VGA output, sprites, etc. This hw can be used for existing machines.

And later can be used this core in the full FPGA EP project.

Offline Saint

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Re: Enterprise VHDL
« Reply #3 on: 2012.September.19. 18:21:28 »
I've had a chat with an ASIC engineer friend of mine, and getting the Nick & Dave chips removed and socketed on the motherboard isn't a big deal, apparently. At least for someone who knows what they are doing!

So it's time to brush up on my VHDL, try doing a hardware sprite add-on, and see where that goes. :)

I'll need to be fairly confident I can do something useful before risking my old Enterprise.

Offline Saint

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Re: Enterprise VHDL
« Reply #4 on: 2012.September.20. 12:27:15 »
Trying to figure out how the hardware hangs together by looking at the Enterprise 64 schematics.

The Nick address bus (a0-15) is insulated from the main address bus through 2 x 74LS244 octal buffers. Nick is connected to the output pins of the octal buffers and the main address bus to the input pins.

The main data bus (d0-d7) is insulated from the Nick data bus through a 74LS245 octal bus transceiver. Nick on port B, data bus on port A.

The direction of the data bus (245) is controlled by Z80 /RD. When Z80 reads A=B, otherwise B=A.

Output enable for address bus and data bus isolation are driven from the Nick /ACCESS line. The access line is controlled from /VRAM and /VIO inputs?

The 64K internal RAM is connected directly to the Nick address bus (which is why Nick can only access this RAM and not external RAM).

The 16bit Nick address bus is multiplexed into row and column (a0-a7 / a8-a15) by two 74ALS158 chips. The row and column bits are fed into the 4164 through toggling RAS / CAS and results in 1 bit being read or written. The nick data bus d0-d7 is fed one bit from each chip.

So essentially the Nick and VRAM are entirely isolated from the main bus.

The RAM access seems to be from an 8MHz clock (8M)? There is also D8M which appears to be a delayed version of the clock – not sure of the delay from 220R and 82pf? Or what this is used for?

Also, is the Nick clocked at 14Mhz exactly? If so we’d have 896 cycles per 64us scanline at 14Mhz, and 512 cycles at 8Mhz (the two clocks into Nick).

Why are there 57 slots available for Nick read in one scanline?

When is the Z80 made to wait on bus access?

I’m very interested to know the bus access scheme for the Enterprise as it will help me understand how the Nick memory access is Interleaved with the Z80 access.

Any thoughts on this much appreciated (mostly from Zozo I expect!) :)


James

Offline Saint

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Re: Enterprise VHDL
« Reply #5 on: 2012.September.20. 12:46:23 »
Actually, bus timing like this might make sense:

| | | | | | |    14MHZ
|   |    |   |    8MHZ

Bus access for Z80 is every 4 8Mhz clock cycles, setting the address on cycle 0 and reading / writing the data on cycle 1. This leaves cycles 2 and 3 empty.

Bus access for Nick is on cycles 3/4 5/6 of the 7 cycles taken at 14Mhz. Setting the address and receiving data twice -- which makes sense for the Nick reading two bytes per slot.

This does give 64 slots per scanline, though. I guess it doesn't use 7 of them??

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #6 on: 2012.September.20. 13:26:37 »
Quote
(mostly from Zozo I expect!) :)
I think IstvanV know the most about the Nick operation, because He has studied the most for made the ep128emu 99.999...% accurate!


The 16bit Nick address bus is multiplexed into row and column (a0-a7 / a8-a15) by two 74ALS158 chips. The row and column bits are fed into the 4164 through toggling RAS / CAS and results in 1 bit being read or written. The nick data bus d0-d7 is fed one bit from each chip.
These can be replaced by 64K SRAM :-)

Quote
So essentially the Nick and VRAM are entirely isolated from the main bus.
Yes. Only connected when the Z80 want access it.

Quote
The RAM access seems to be from an 8MHz clock (8M)? There is also D8M which appears to be a delayed version of the clock – not sure of the delay from 220R and 82pf? Or what this is used for?
Interesting question! I guess it is used for RAS/CAS delays. On 6 or 7.12Mhz turbo machines sometimes needed to short circuit the resistor, and remove the capacitor.

Quote
Also, is the Nick clocked at 14Mhz exactly?
No, it is a 14237536.27 Hz, there is IstvanV calculations.

Quote
Why are there 57 slots available for Nick read in one scanline?

I guess because the target is a standard 40/80 column character mode with some border. First 8 slot used for reading LPT, last 3 used for VRAM refresh, 46 slot remaining for displaying. The EXOS use default 40 for displaying, but possible to use 42. These are fill the screen at the old tvs from the '80 years. With machine code programs can be used all 46 (no border), modern monitors and tvs can be display it.

Quote
When is the Z80 made to wait on bus access?
The Nick make the System Clock/2 for the Z80, and when the Z80 want to access the VRAM and the Nick is also, then the Z80 clock is paused. The wait is 1-5.5 Z80 cycle on 4Mhz machine dependig when tryd the Z80 accessing the video part.
Not documented, but the Nick I/O port access is also generate Z80 waits.
In one video slot 2 bytes readed by Nick, and 1 free for the Z80.

(The Dave is also can make Z80 wait cycles, programed at the BFh port, these use the WAIT signal of CPU)

« Last Edit: 2012.September.20. 13:30:56 by Zozosoft »

Offline Saint

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Re: Enterprise VHDL
« Reply #7 on: 2012.September.20. 14:21:16 »
Ahh, this is interesting that the Nick is not 14Mhz. By straight calculation, it should have been 14.25MHz (as IstvanV says), but it's different.

I guess the 14.xxx MHz clock comes from that small chunk of circuitry on the schematic connected to the 14M line which I do not understand at all, as there are only 2 crystal cans on the PCB. I guess that's a "Phase Locked Loop"? My electronics is not brilliant. :)

So, running code from outside the VRAM will be faster than from inside VRAM, due to reduced wait states.

Ok, starting to understand things a little better. :)

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #8 on: 2012.September.20. 14:37:47 »
By straight calculation, it should have been 14.25MHz (as IstvanV says), but it's different.
IstvanV says it is not 14.25!
I try to translate the calculation:
The Nick is using 284 colour carrier instead the standard 283.75.
One scanline is 57 slot (character).
- Colour carrier freq: fPAL = 17734475 / 4 = 4433618.75 Hz
- line freq: fPAL / 284 = 15611.33 Hz (instead the standard 15625)
- character freq = fPAL * 57 / 284 = 889846.02 Hz
- NICK input clock = fPAL * 57 * 16 / 284 = 14237536.27 Hz
- screen freq = fPAL / 284 / 312 = 50.0363 Hz (instead the standard 50 Hz)

Quote
I guess the 14.xxx MHz clock comes from that small chunk of circuitry on the schematic connected to the 14M line which I do not understand at all, as there are only 2 crystal cans on the PCB. I guess that's a "Phase Locked Loop"? My electronics is not brilliant. :)
Yes it is a PLL.
IstvanV guess on the H2 output is the input clock / 1824 (16*57*2).

Quote
So, running code from outside the VRAM will be faster than from inside VRAM, due to reduced wait states.
Yes! This is the main reason why the EP128 faster then the EP64.
And some early games which is writed to EP64 (for example Tombs of Doom) is tooooooo... fast on EP128 :-)

Offline Saint

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Re: Enterprise VHDL
« Reply #9 on: 2012.September.20. 15:57:00 »
The Nick causing wait states is interesting. This did not happen on the Atari ST, the hardware I am most familiar with (well, not to any real extent!), although I am aware of this on other machines. On the ST the bus cycles were interleaved to allow video and cpu to access the RAM without slowdown (hence my previous thought on how it worked).

So I'm guessing the /VIO pin on Nick is an output to tell Dave when the video RAM is being accessed so the /WAIT line can be controlled accordingly?

Edit: Ah, sorry, I re-read the earlier post. The Z80 clock is actually delayed -- very interesting!!
« Last Edit: 2012.September.20. 16:11:50 by Saint »

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #10 on: 2012.September.20. 16:46:05 »
So I'm guessing the /VIO pin on Nick is an output to tell Dave when the video RAM is being accessed
No!
The DAVE is the address decoder for all things on the mother board.
The VIO is active when video ports (80-8fh) accessed. And the VRAM when the top 64K of the 4M memory accessed (FC-FFh segments, 3F0000-3FFFFFh phisycal address).
Dave documentation.

Offline Saint

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Re: Enterprise VHDL
« Reply #11 on: 2012.September.22. 08:57:05 »
Does anyone know how the z80 clock is delayed by Nick?

It would be really useful to have a scope trace of 8m, 14m, mreq and z80 clock.

I guess the z80 is delayed during mreq while the nick is accessing ram. But what if the z80 is already performing a read when nick wants access?

I need to get myself a scope!!

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #12 on: 2012.September.22. 10:19:20 »
I need to get myself a scope!!
In October, I plan to buy one!

Offline Saint

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Re: Enterprise VHDL
« Reply #13 on: 2012.September.23. 08:29:51 »
« Last Edit: 2012.September.23. 09:00:31 by Saint »

Offline Zozosoft

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Re: Enterprise VHDL
« Reply #14 on: 2012.October.08. 23:03:46 »
First try to measure clocks:

8Mhz system Clock and 4Mhz Z80 clock:
8157-0

8Mhz system Clock and 4Mhz Z80 clock while running NOPs in video memory:
8159-1

14Mhz Nick clock and 8Mhz system Clock:
8161-2

14Mhz Nick clock and 4Mhz Z80 clock while running in normal memory:
8163-3

14Mhz Nick clock and 4Mhz Z80 clock while running NOPs in video memory:
8165-4

14Mhz Nick clock and 6Mhz Z80 clock while running NOPs in video memory:
8167-58169-6

14Mhz Nick clock and 7.12Mhz Z80 clock while running NOPs in video memory:
8171-7
« Last Edit: 2012.October.08. 23:24:35 by Zozosoft »