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Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 42401 times)

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #240 on: 2022.May.02. 13:23:33 »
Dr.OG: I think you know György Szombathelyi ( slingshot ) ( Gyurco ) from Atari-forum.
I'm mentioning this because when Kyp and Rampa make the source code public, it's possible that he could make a port attempt to MiST / SiDi.

The biggest problem with these FPGAs is that they have very little BRAM (about 68KB), which is insufficient for this core to work. No problem with the cells, there's plenty of room.

Slingshot has previously ported cores like the ZX Next, so it has a great command of those instantiated in SDRAM. The same he can make it work so that all users of these FPGAs benefit.

And if not to wait a bit, since Kyp has some ideas to make it possible.

Anyway, enjoy the Enterprise on FPGA. Cheers

Offline Dr.OG

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #241 on: 2022.May.02. 15:35:11 »
Thank You! I pointed previously Gyurco's attention to this project, as soon as the source code will be available, he will investigate the option of porting. He migrated the SNES and Sega Genesis/Megadrive cores formerly, so I doubt that EP core could cause serious problems...
ÉN ekelek, TE keregsz, Ő gyeleg,
MI ákolunk, TI vornyáztok, ŐK lendeznek.

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #242 on: 2022.June.17. 22:34:11 »
Hello. I've recently tried loading some games from tape and found that it doesn't work. Since the implementation of the SD card I had not tried. I think is something related to interrupts and sound.

Is there any difference between how 1KHz/50Hz timers and tome0/tine1 timers are treated? I am treating all the same. I have one counter and one flip-flop. The counter counts down from 250/5000/period0/period1 to 0, as specified in bits 6:5 of reg A7, and when it reaches 0 the flip-flop changes it state and interrupt 0 is triggered and is active until a 1 is written to bit 1 of reg B4.

What happens if sync of tone is high? The flip-flop changes when 0 is reached or when the count starts after sync goes low?

How is related audio interrupts and tape loading?

Any help would be really appreciated. Thanks!
« Last Edit: 2022.June.17. 22:54:14 by Kyp »

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #243 on: 2022.June.18. 18:45:59 »
Probably Bruce or Zozo can help, they know how EXOS loads from tape. :)

I checked the Dave addons by IstvánV.
A7h port
    b0-b2: sync on (high means)
        the counter of belonging channel is not running
        the counter is hold continuously on frequency values are set in A0h-A5h registers
        flip-flip of tone generator output is set to 0
    b5-b6: the interrupt is driven by the counter of belonging tone generator (not the modified (filtered, distorted)), after each run to 0 bit0 of B4h port change, and (if interrupt is enabled) bit1 is set.
1KHz interrupt is equal to 250-1 tone generator frequency, and 50Hz is equal to 5000-1, so it differs from the video interrupt, it 80000 Z80 T-State (or 120000 if bit1 of port BFh is set)

I saw that all Dave interrupt is set during loading, but i think only Dave programmable interrupt is used during reading tape signal, and sync bit set/reset, and when 4 KB chunk is loaded then it changes to 50Hz Dave interrupt, and when tape read starts again it is on 1000Hz dave interrupt, but after some instructions it changes to programmable interrupt with tone0 sync high and wait until signal starts, if it is started then it release sync bit, and reset Dave interrupt (ld a,03h  , out (0b4h),a  )
« Last Edit: 2022.June.18. 18:58:41 by geco »

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #244 on: 2022.June.19. 17:01:12 »
Thank you again :)

Then...

If sync is 1 the counter of belonging channel is not running? Also in the middle of the count? Or only at the end?
Flip-flip of tone generator output is set to 0 at the end of the count?

I have to read the last paragraph carefully :)

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #245 on: 2022.June.21. 17:37:11 »
Thank you again :)

Then...

If sync is 1 the counter of belonging channel is not running? Also in the middle of the count? Or only at the end?
Flip-flip of tone generator output is set to 0 at the end of the count?

I have to read the last paragraph carefully :)
As i understand, when sync bit set, it stops immediately the counter of the channel, and the counter is hold ony frequency value which is set by it's belonging tone registers (a0h-a5h)