Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 58403 times)

ron · « **Reply #120 on:** 2020.December.18. 13:45:53 »

Hi Folks !

At this moment we already have the core working in BRAM (256K ram ) and SRAM (1 MB ram) made by Yo_Me. (Works for MiSTer)
EXOS 2.4 + EXDOS + ISDOS and whatever the ROMS setting. Kyp is finishing rewriting the Nick as he felt he could improve it, although right now we have the old version working which works perfectly.

So, rampa is racking his brain with the disk controller. The EXDOS disk controller is already working and the first directory is very close. We are having some problems because when reading discs it tells us that NOT A DOS DISK.
We are working to find out if it is a question of timers or is it because Dave lacks some implementation, in principle the controller communicates with the enterprise but refuses to read the disks.

To say that any help is very much appreciated, if you can tell us what the enterprise does when requesting the reading of the floppy, there is something that escapes us and we will try to find it.

Enterprise Deployment Attempt Over FPGA.

Regards, ron

BruceTanner · « **Reply #121 on:** 2020.December.18. 16:01:00 »

Hi Ron,

When you first go :dir EXDOS will try and read the first sector ie. side 0 track 0 sector 1, the "boot sector", although EXDOS does not actually boot from it (note sectors are numbered from 1 not 0

). If there is a WD1770 error the read operation will be retried but eventually EXDOS will give up and report the error to the user.

If the boot sector is successfully read (ie. no WD errors) then EXDOS checks the data in the sector for various file system features which should be present on a MS-DOS type disk. "Not a DOS disk" means one of these features is not present.

But all the above assumes a formatted disk. From your screen shot it looks as though the first problem is that you cannot format it, and get a "Not ready" error? The first thing :format does is lots of head steps in and out to work out if it is a 40 or 80 track drive. Then it does a WD1770 "Read Address" command, which could cause a Not Ready error, could this be the problem? It does not matter what data is read - EXDOS is doing this just to test if there is a disk in the drive - Not Ready means no disk. After the Read Address is successful it should start doing WD Write Track commands to format the disk.

B.

gflorez · « **Reply #122 on:** 2020.December.18. 16:07:03 »

Thanks Bruce!

ron · « **Reply #123 on:** 2020.December.18. 18:02:18 »

OK Bruce, let's taka a look !
Thank You

keyboardjunkie · « **Reply #124 on:** 2021.February.13. 17:32:56 »

Hi folks,

I've just stumbled across this thread and am amazed at the progress here!

I wondered (since the last post in the thread was back on 18/12/2020) if there were any further updates from the team on this project? It is fascinating reading and I would love to be able to try this out on my Mister..

Please keep up the great work!

KbJ

ron · « **Reply #125 on:** 2022.January.14. 21:20:47 »

Tonight starting at 10 pm, we are going to premiere Kyp's core live. This is a very preliminary version but it already has SD support.

We are still working on the disk controller.

You can see the stream, in Spanish on Twitch: https://www.twitch.tv/retrocrypta

A lot of thanks to rampa069, GFlorez and Kyp by the effort

geco · « **Reply #126 on:** 2022.January.15. 09:11:34 »

Cool, keep on the great work

I wait the FPGA EP.

MrPrise · « **Reply #127 on:** 2022.January.15. 12:42:49 »

Whoa, nice!

Tuby128 · « **Reply #128 on:** 2022.January.15. 16:23:49 »

Quote from: ron on 2022.January.14. 21:20:47

(Attachment Link)

Tonight starting at 10 pm, we are going to premiere Kyp's core live.

You can see the stream, in Spanish on Twitch: https://www.twitch.tv/retrocrypta

At time 41:50, as the "VERP" closes and IS-BASIC starts. The size of the free memory is very low for my eyes.

A fenti idôpontnál a videóban, ahol "VERP" véget ér és IS-BASIC elindul, a szabad memória mérete eléggé kevés az én szememnek.

Tuby128 · « **Reply #129 on:** 2022.January.15. 16:33:53 »

I was watching the Raid over Moscow at about 49:00 and I can clearly see a problem with the horizontal scroll.
I am curious what horizontal SYNC frequency the FPGA produces. Is it the original 15 khz?

I would suggest to test EXOLON 1 game.
This is very special. The vertical resolution is about 100 lines, and every line has a record in the NICK Line Parameter Table.
It uses Spectrum-type attribute mode graphics.

Kyp · « **Reply #130 on:** 2022.January.15. 22:03:49 »

Quote from: Tuby128 on 2022.January.15. 16:33:53

I was watching the Raid over Moscow at about 49:00 and I can clearly see a problem with the horizontal scroll.
I am curious what horizontal SYNC frequency the FPGA produces. Is it the original 15 khz?

The pixel clock is currently 14.0000 MHz. I know it should be 14.2375, but it's hard to produce such exotic clocks from the FPGA PLL.

Quote from: Tuby128 on 2022.January.15. 16:33:53

I would suggest to test EXOLON 1 game.
This is very special. The vertical resolution is about 100 lines, and every line has a record in the NICK Line Parameter Table.
It uses Spectrum-type attribute mode graphics.

It works

(Yes, I know, there is a problem with the last pixels in every line

but it happens always in this video mode)

)

Tuby128 · « **Reply #131 on:** 2022.January.16. 08:33:55 »

Try to do the following use a PLL to convert your base 50MHz or whatever base frequency to 100MHz. And divide it with 7, which makes 100/7= 14,2857 MHz
If the devider with 7 is not supported in the PLL, you can make an async logic divider as well.

Anyway, are you using Altera (intel) or Xilinx FPGA? Verilog or VHDL?

Kyp · « **Reply #132 on:** 2022.January.16. 17:29:55 »

It's not that easy, in addition to the 14.xxx clock you have to get the 16,000 MHz one and there is no MUL/DIV combination that produces both.

I can use two PLLs, but most modules are designed to use a common high-frequency clock with clock-enables and this is not compatible with clocking from different PLLs.

Anyway, I prefer to complete the implementation first and then refine it. There is still a lot of work to do.

Tuby128 · « **Reply #133 on:** 2022.January.16. 17:35:03 »

I don't understand you, because I did not see your FPGA schematic circuit, can you show me please.

Kyp · « **Reply #134 on:** 2022.January.16. 21:45:48 »

It is a neptUNO board:
https://github.com/neptuno-fpga/Main_nepUNO/wiki

Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 58403 times)

ron

Re: Enterprise Deployment Attempt Over FPGA.

BruceTanner

Re: Enterprise Deployment Attempt Over FPGA.

gflorez

Re: Enterprise Deployment Attempt Over FPGA.

ron

Re: Enterprise Deployment Attempt Over FPGA.

keyboardjunkie

Re: Enterprise Deployment Attempt Over FPGA.

ron

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geco

Re: Enterprise Deployment Attempt Over FPGA.

MrPrise

Re: Enterprise Deployment Attempt Over FPGA.

Tuby128

Re: Enterprise Deployment Attempt Over FPGA.

Tuby128

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Kyp

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Tuby128

Re: Enterprise Deployment Attempt Over FPGA.

Kyp

Re: Enterprise Deployment Attempt Over FPGA.

Tuby128

Re: Enterprise Deployment Attempt Over FPGA.

Kyp

Re: Enterprise Deployment Attempt Over FPGA.