Welcome, Guest. Please login or register.


Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 13572 times)

Offline geco

  • EP addict
  • *
  • Posts: 5972
  • Country: hu
  • OS:
  • Linux Linux
  • Browser:
  • Chrome 86.0.4240.99 Chrome 86.0.4240.99
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #105 on: 2020.October.25. 07:11:19 »
Incredible effort !!!

Online Trefe

  • User
  • *
  • Posts: 55
  • Country: hu
  • OS:
  • Windows NT 10.0 Windows NT 10.0
  • Browser:
  • Firefox 81.0 Firefox 81.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #106 on: 2020.October.26. 19:15:07 »
Amazing. :shock:  Does this work for SIDI?

Offline gflorez

  • EP addict
  • *
  • Posts: 3094
  • Country: es
  • OS:
  • Windows 7/Server 2008 R2 Windows 7/Server 2008 R2
  • Browser:
  • Firefox 81.0 Firefox 81.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #107 on: 2020.October.26. 20:58:57 »
Yes, Mist, Sidi, Mister, etc. The development is being done on a ZXUNO, with a smaller FPGA, and then converted to the other ones.

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 82.0 Firefox 82.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #108 on: 2020.October.27. 07:17:26 »
There is a small hurdle to overcome in MiST. The MiST needs Quartus 13 to synthesize the cores, and instead both MiSTer and SiDi use the Quartus 17 versions. Our preferred manufacturer (manuferhi.com) will port to MiST. Actually I would love for the MiST port to be a success.

Remember that SiDi carries a Cyclone IV and the MiST a Cyclone III, yes, both have similar characteristics, memory, cells, but it is much easier to port to SiDi right now than to MiST.

Regarding the state of the core right now. You have to finish the Nick and start preparing the Dave. Later, depending on how the BUS can be implemented, it is necessary to think about either the disk controller or the SD-Card.
It shouldn't be a problem to equip the core with up to 4 MB of ram. Right now the audio upload works very well in ZXUNO but in MiSTer it is giving some problems due to the DAC converter.

We will keep you informed, thanks for all the support.

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #109 on: 2020.December.01. 22:39:38 »
Hi, Disk controller is comming
Soon more news...





Offline Dr.OG

  • EP user
  • *
  • Posts: 326
  • Country: hu
  • dr.
  • OS:
  • Windows NT 10.0 Windows NT 10.0
  • Browser:
  • Chrome 86.0.4240.198 Chrome 86.0.4240.198
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #110 on: 2020.December.02. 05:49:06 »
WOW! Incredible! I can't wait to test it!
ÉN ekelek, TE keregsz, Ő gyeleg,
MI ákolunk, TI vornyáztok, ŐK lendeznek.

Online Trefe

  • User
  • *
  • Posts: 55
  • Country: hu
  • OS:
  • Windows NT 10.0 Windows NT 10.0
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #111 on: 2020.December.02. 16:43:38 »
WOW! I want a SIDI. Later... :-)

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #112 on: 2020.December.03. 08:41:02 »
Hello, how are you there?, some news for today.

Just a nuance, for the MiST, MiSTica and SiDi boards there is a small drawback. They do not have SRAM, since the RAM they have is SDRAM. Be patient that it is only a matter of time.

In BRAM these FPGAs have approximately 60 or so KB and between the VRAM and the OSD it will possibly be achieved, although it will take work.

Currently the development continues, on the one hand Nick is being rewritten and on the other hand finishing the Dave implementation. In addition to the EXDOS Controller that is very close to going live.

Finally a WD1772 has been implemented and there are still tests to be done, when I have more news I will let you know.

Cheers

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #113 on: 2020.December.09. 19:09:11 »
Hi there ! Gentlemen ! Some Help and advice needed.

We're having some trouble implementing the WD1772 EXDOS Controller. We would like to know : In what condition does the "controller not ready" error occur and what does it look for to get the 193 exdos1.4 error ?

in theory the 1.4 goes fixed over the range 0x10-0x13 + 0x18

In a new approach we have used the rom EPDOS1.9 together with EXDOS 1.3, which lacks the 193 error, but the controller keeps crashing.

How does enterprise know that the controller is connected, do we know the ports and signals?, is not clear at all. We need a bit more information.







Any help is greatly appreciated, thank you very much.

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #114 on: 2020.December.09. 19:30:19 »
Here one more screen with DEVS ( EPDOS ) output:

Offline BruceTanner

  • EP lover
  • *
  • Posts: 556
  • Country: gb
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #115 on: 2020.December.09. 21:23:22 »
In what condition does the "controller not ready" error occur and what does it look for to get the 193 exdos1.4 error ?
It outputs test values to ports 11h and 12h, and checks that the values can be read back at 15h and 16h (ports 10h-13h are mirrored at 14h-17h if the EXDOS card is there.) The test values are 55h and aah but then the test is repeated with the values swapped ie. aah and 55h.

Code: [Select]
; Return Z if an EXDOS card is there, NZ if no EXDOS card
WDCHECK: LD A,55H
OUT (11H),A
LD A,0AAH
OUT (12H),A
PUSH BC
PUSH BC
POP BC
POP BC
IN A,(15H)
CP 55H
RET NZ
IN A,(16H)
CP 0AAH
RET NZ
LD A,0AAH
OUT (11H),A
LD A,55H
OUT (12H),A
PUSH BC
PUSH BC
POP BC
POP BC
IN A,(15H)
CP 0AAH
RET NZ
IN A,(16H)
CP 55H
RET

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #116 on: 2020.December.09. 21:41:05 »
Thanks a LOT Bruce !
Giving it a try !

Offline BruceTanner

  • EP lover
  • *
  • Posts: 556
  • Country: gb
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #117 on: 2020.December.09. 22:24:01 »
I should add that the EXDOS code relies on the port 10h-13h mirroring at 14h-17h for actual operation, not just for testing whether the EXDOS card is there! :lol:

These days the EXDOS card is always at 10h-13h (and 14h-17h :mrgreen:) but originally there was a expansion card scheme that meant the EXDOS card could be at 20h-23h, or 30h-33h, or.... So all I/O is done through IN r,(C) and out (C),r instructiions. During sector reading and writing, to get C from pointing to the WD1770 data port at 13h to the status port at 10h very quickly, and then back to the data port again, the code uses INC C/DEC C, thus relying on the port mirroring!

B.

Offline ron

  • User
  • *
  • Posts: 60
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 83.0 Firefox 83.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #118 on: 2020.December.09. 22:31:20 »
Thanks again, very helpful!
We already have the mirroring of the ports, at this moment we only need the fdc to respond, we will see what it says in the tests.

Offline C5484

  • EP fan
  • *
  • Posts: 183
  • Country: hu
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 76.0 Firefox 76.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #119 on: 2020.December.17. 17:01:13 »
This is great!

I hope i can test the Enterprise 128 core on my MiSTer soon!