Welcome, Guest. Please login or register.


Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 4385 times)

Offline elmer

  • User
  • *
  • Posts: 56
  • Country: us
  • OS:
  • Windows 7/Server 2008 R2 Windows 7/Server 2008 R2
  • Browser:
  • Firefox 79.0 Firefox 79.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #60 on: 2020.August.18. 19:36:45 »
I say this just for information, not to criticize, I am in awe at people's ability to use English on this forum :bow: it puts my language skills to shame :oops: :oops: :oops:

I agree, I'm amazed at all of the posts in English from people for whom it is a 2nd or 3rd language. It makes me ashamed of my poor language skills.

I'm really glad to hear that the development is continuing. :-)

Offline szipucsu

  • EP addict
  • *
  • Posts: 8584
  • Country: hu
  • OS:
  • Windows 7/Server 2008 R2 Windows 7/Server 2008 R2
  • Browser:
  • Firefox 79.0 Firefox 79.0
    • View Profile
    • Webnyelv.hu - Tanuljunk nyelveket!
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #61 on: 2020.August.18. 21:04:01 »
hardly and hard can be used as equivalents
I think they cannot be used as equivalents. But you are right saying "hardly" means "very-very little" or "almost not". As I know "hardly" can have nothing to do with "hard". But correct me if it is not true.
(Hard - hardly are exceptions. A lot of other words like this have similar meanings, e.g. soft - softly or happy-happily.)
100 SOUND SOURCE 3,STYLE 16,LEFT 16,RIGHT 64,SYNC 2
110 SOUND SOURCE 2,STYLE 128,PITCH 25.2,SYNC 2
120 SOUND PITCH 25,SYNC 2
Videos

Offline gflorez

  • EP addict
  • *
  • Posts: 2931
  • Country: es
  • OS:
  • Windows 7/Server 2008 R2 Windows 7/Server 2008 R2
  • Browser:
  • Firefox 79.0 Firefox 79.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #62 on: 2020.August.18. 22:51:51 »
Apologies.... You all are right....

When I have received my friend's message I was doing shopping. I was eager for sharing it after so much time without news, so I have put the Spanish text on google and directly to this forum the translation.... My own text also was defective, so I also have some culpability....

Later, still shopping... I have read the answers and I have tried to change the sense of my earlier commentary.... and maybe some of you have been offended.


Yes I wanted to mean "working hard", not "hardly working". Some times on Spanish the order of the adjective is not significant on the sentence, and this is one of these cases: "duro trabajo" and "trabajo duro" is practically the same.

Also, the meaning of "último"("last") is not so definitive as in English, it is only the more recent in a succession of events, not the last of this era, never, the end, etc.

So yes, the development continues. Kyp means that the Enterprise chips will be the harder part to implement and trim, but there is a team behind to support him..


Offline ergoGnomik

  • EP lover
  • *
  • Posts: 949
  • Country: hu
  • Stray cat from Commodore alley
  • OS:
  • Windows NT 10.0 Windows NT 10.0
  • Browser:
  • Firefox 78.0 Firefox 78.0
    • View Profile

Offline Kyp

  • Newbie
  • Posts: 2
  • OS:
  • Windows NT 10.0 Windows NT 10.0
  • Browser:
  • Firefox 80.0 Firefox 80.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #64 on: 2020.September.07. 13:35:35 »
I've been busy with other things but the project is still alive. Be patient.

I have a question.

ROM boot test doesn't show CPU speed, I think it's because I haven't implemented interrupts yet. I'm right? Well I just wired the VSYNC interrupts directly to the INT signal of the CPU, but I guess it's not correct. I'm not sure about how interrupts work in general. I have read about Dave's registers, but I am not sure how they work. For example, what is connected to INT1 or INT2?

Offline geco

  • EP addict
  • *
  • Posts: 5728
  • Country: hu
  • OS:
  • Linux Linux
  • Browser:
  • Chrome 84.0.4147.111 Chrome 84.0.4147.111
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #65 on: 2020.September.07. 18:37:11 »
yes, the cpu speed is calculated based on numbers of 1KHz Dave interruts within 1 50Hz Nick interrupt. Dave speed is increasing with the CPU speed.

Offline geco

  • EP addict
  • *
  • Posts: 5728
  • Country: hu
  • OS:
  • Linux Linux
  • Browser:
  • Chrome 84.0.4147.111 Chrome 84.0.4147.111
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #66 on: 2020.September.07. 18:41:55 »
as i saw Nick interrupt is on int1, and nothing on int2

Offline dangerman

  • User
  • *
  • Posts: 67
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 79.0 Firefox 79.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #67 on: 2020.September.12. 11:00:49 »
as i saw Nick interrupt is on int1, and nothing on int2

It's been a while but I seem to remember that int2 is connected to the network port, so that networked Enterprises can be alerted if another machine is sending data.

Offline dangerman

  • User
  • *
  • Posts: 67
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 79.0 Firefox 79.0
    • View Profile
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #68 on: 2020.September.12. 11:19:17 »
Well I just wired the VSYNC interrupts directly to the INT signal of the CPU, but I guess it's not correct. I'm not sure about how interrupts work in general. I have read about Dave's registers, but I am not sure how they work. For example, what is connected to INT1 or INT2?

On the Enterprise, interrupts are connected to the DAVE chip and then DAVE controls the INT signal of the CPU. Interrupts are latched by DAVE so they can get passed to the CPU (eventually) even if they occur when Z80 interrupts are temporarily disabled.

DAVE has 4 sources of interrupts...

1. Variable frequency interrupt - either 50Hz, 1kHz or a variable frequency specified by the tone generator (ie the pitch of sound)
2. An interrupt at 1Hz
3. INT1 - this is connected to the Nick chip interrupt
4. INT2 - I think this is connected to the network port, so you probably don't need to worry about it.

You can find out what interrupts have occurred by reading DAVE register $B4.
You enable/disable the different interrupt sources and clear interrupt latches by writing to DAVE register $B4.

Offline ron

  • Beginner
  • *
  • Posts: 38
  • Country: es
  • OS:
  • Linux (Ubuntu) Linux (Ubuntu)
  • Browser:
  • Firefox 80.0 Firefox 80.0
    • View Profile
    • RetroWiki & Cacharreo [RW]
Re: Enterprise Deployment Attempt Over FPGA.
« Reply #69 on: 2020.September.21. 23:25:29 »
All info about Enter interruptions is very appreciated.
The core is getting a great shape. :-)

See you soon. Regards-.