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Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 2878 times)

Online gflorez

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #15 on: 2020.May.07. 12:22:24 »
Thanks ergoGnomik.

Yes, there are invaluable documents on Zozo's page. I hope that the geniuses on the project could translate all that little boxes on the design.

The sheets seem to be modified on some parts. If they are effectively the latests revisions E and D(the fixed NICK?), maybe they will lead to a good implementation of the chips.

Offline dangerman

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #16 on: 2020.May.07. 12:49:15 »
These links are extracted from the official Nick and Dave documents that we are already managing. Do they have any fixing over the originals?

Great stuff. Those will probably be the best place to start. I'm not totally sure but I don't believe there are any fixes in the HTML version.


Offline Tutus

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #17 on: 2020.May.07. 13:13:49 »
Greetings to all users and lovers of the Elan Enterprise.
The main objective is to achieve an Enterprise 128 implementation that works on FPGA boards like MiST, MiSTica and SiDi and so that later FPGAs like the MiSTer can be ported.

Hi ron!

We also had such a plan two months ago, but due to lack of money and specialist, we gave it up ...
So, yours is the "track", if we can help you with anything, let me know!
We have a Hungarian Enterprise Club community behind us. You can count on us! :)
« Last Edit: 2020.May.07. 13:17:20 by Tutus »

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #18 on: 2020.May.08. 09:04:28 »
Thank You very much !

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #19 on: 2020.May.09. 22:25:55 »
Hi there, fellows !

We have some progress, much more than we could expect. Our friend rampa069 has not given us time nor to assimilate all that he has already managed to do. Amazing !

Because the FPGA's SDRAM has 24 addressing bits, rampa069 has successfully reduced the Enterprise MMU in a very smart way. First 8 bits (Content of the port pointed to by the two high lines as a bank) +2 bits (The active port (B0, B1, B2, B3)) + 14 low bits of the address bus..., as soon as a Pseudo_NICK can start painting, there are a lot of possibilities that it will start working right away.

So, Kyp is redoing the control signals but since kyp uses a 28MHz master clock,  with clock enables it is more messy. There are a lot of clocks out of combinatorics and that doesn't like the FPGA. The advantage of FPGA implementations is that as milestones are achieved, you can start testing.

Now ROM loads OK, just using a EP128.ROM file at SD's root in where you can concatenate all ROMS you want. It loads from SD at address 0.-

Also the disc controller is working.

24674-0
24676-1

Surely tonight ramp069 will enable the Git and all the part already converted to EP128 will be deployed. More or less these are the news we have, it seems that everything is going faster than expected.



Best Regards
ron
« Last Edit: 2020.May.09. 23:06:57 by ron »

Offline Dr.OG

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #20 on: 2020.May.10. 05:28:40 »
Good news! :smt041 :smt038
That was quick!!!
ÉN ekelek, TE keregsz, Ő gyeleg,
MI ákolunk, TI vornyáztok, ŐK lendeznek.

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #21 on: 2020.May.11. 07:30:14 »
... and pseudo-Nick started painting.


Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #22 on: 2020.May.11. 08:20:04 »
Cool :smt041

Offline Zozosoft

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« Last Edit: 2020.May.11. 11:32:54 by szipucsu »

Online gflorez

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #24 on: 2020.May.11. 10:40:01 »
Thanks, Zozo. Now they are working more with the timings that these 2 documents describe.

Offline Zozosoft

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #25 on: 2020.May.11. 13:55:11 »
Another important thing: clocks calculations by IstvanV

Offline Zozosoft

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Online gflorez

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #27 on: 2020.May.11. 15:13:44 »
Great! Thanks Zozo.

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #28 on: 2020.May.11. 20:06:44 »
After the improvements, the pseudo Nick says HELLO! and you already use the EXOS font


Online gflorez

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #29 on: 2020.May.11. 20:29:49 »
24698-0

@Kyp:

"No solo se ve, está 'procesando' la LPT, leyéndola de la RAM. En esa imagen están las dos bandas del borde superior e inferior, 28 bandas en modo CH128 (cambiando el puntero a donde empieza el texto) y las dos bandas en modo VSYNC para el sincronismo vertical :grin: "

----

"It not only sees, it is 'processing' the LPT, reading it from Ram. In  this image there are the two bands, upper and lower, 28 bands in CH128 mode (modifying the pointer where starts the text) and the two bands on VSYNC mode for the vertical synchronism :grin: "