Enterprise Forever

:UK => Hardware => Topic started by: ron on 2020.May.05. 11:26:09

Title: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.05. 11:26:09
Greetings to all users and lovers of the Elan Enterprise.

Not long ago, we formed a small team of retro computer enthusiasts and were able to implement several things, including Oric's core with Microdisc. Anyway, in the group there are users with great knowledge of Z80 and Enterprise HW.

Currently we have a fairly solid group and we are open to anyone who can contribute documentation and knowledge.

The main objective is to achieve an Enterprise 128 implementation that works on FPGA boards like MiST, MiSTica and SiDi and so that later FPGAs like the MiSTer can be ported.

Two of the main pitfalls to overcome are the ASICs or Custom:  Nick and Dave, since there is no implementation and all we have are the emulators and the documentation that we all know.

How could it be otherwise, Glorez is on the team as he is one of our best Enterprise ambassadors. GFlorez will be our interface with EntepriseForEver and RetroWiki and the Telegram group.

Without haste but without pause, no matter how long it can consume, it is something done totally altruistically, unconditionally and without any kind of profit.

We have to focus our efforts to get the best possible implementation from Nick and Dave. It is key, because the rest of the core is more or less already defined.
The first things we need is to have the Nick's Video base to start painting on the screen and gradually add all the development. Dave's part seems more affordable.

We hope you find this project interesting and we invite you to participate. We will create a thread in Spanish on RetroWiki to be able to exchange knowledge and impressions.

This is all for now, we will inform you promptly and we hope you like it.

Best Regards.
ron.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.05. 11:45:47
Here is the post at RetroWiki in Spanish:
http://www.retrowiki.es/viewtopic.php?f=108&t=200035693

Saludos !
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.May.05. 13:49:08
Great news, if it is ready, i will interested about buying a hw :)
Zozo posted schematics of Nick few days ago somewhere in the forum, and probably source of IstvánV's great EP128emu (https://github.com/istvan-v/ep128emu) can help a lot.
As i know there is a HW project also in Hungary where EP is included also, unfortunately i do not remember who makes it, i just know i saw the working hw once, but Nick emulation was not perfect.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.05. 14:27:05
Yes, but FPGA is not emulating, it is the real thing implemented inside a programmable chip. Nothing to do with R-Pi emulation.

All the discrete chips of the EP can easily be implemented, but are the ASIC chips, Nick and Dave what are a mystery inside. The designs we have are not the definitive versions.

Of course, IstvanV's great emulator will be invaluable in the task due to the perfection it has achieved. But at the end is the real machine what will be cloned.

All aid will be welcomed in this project, if you find the makers of the Hungarian project, please put them in contact.

Thanks!.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.May.05. 14:35:08
If the project geco is talking about is Z80MU, then that's not a hardware emulator but a software implemented for a custom hardware.

Obviously, ep128emu can't be used as a direct base for VHDL programming, but as it is a cycle-exact emulation, it can be used as an information source of what, when and why happening in those ASICs.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.May.05. 14:52:21
Yes, sorrry, i thought it is a hw stuff.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.05. 15:31:09
I have thought-out.... if this project goes on.... It would be a great enjoyment for the old guy that designed the Nick chip to know about it. Maybe even participate, but this is an open project and involving him has to be considered by all.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.May.05. 16:22:49
Hi!

There are some older topics related to this subject:

https://enterpriseforever.com/hardware/one-chip-msx-mkii-a-chance-for-an-enterprise-in-fpga/

https://enterpriseforever.com/hardware/enterprise-vhdl/

https://enterpriseforever.com/hardver/programozhato-logikai-aramkorok/

https://enterpriseforever.com/hardver/fpga-ep/
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.May.05. 16:28:51
the old guy that designed the Nick chip

I do understand that you had no such intention, but referring to Mr. Nicholas Toop as the old guy seems a bit disrespectful.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.05. 20:23:54
Do you think it? Not for me, and not just when I am writing about how he would enjoy knowing this project. I can't at the same time be insulting him.

Take it as an affectionate nickname, my admiration to a man on that privileged status, a man that has lived intensely and that has a knowledge.

----

But I want to explain the motivations I have when I come here to this web page that I consider my home.

I come here to lean from others, even the most humble user of the page can amaze me with some topic, from the Enterprise or not. I have found here people that have shared their knowledge without asking me how much I know, who I am or from where I come. I think I have acted  the same with others, with courtesy, humour and respect.

Only a short number of members here have the English language as their native language, so it is possible that a British speaker can found a lot of incorrections on the messages we share. That is the reason why we can't take all expressions as literals, because then we could start the Third World War in few seconds

Better let's take the words on the context, reading carefully, forgiving us for the mistakes that we sure make when expressing ourselves. It is only my desire.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.05. 20:49:00
Dr.Og ! very nice ! Thanks for the links. !

I hope no one bothers about a loving nickname. I have no doubt that GFlorez has cited Mr Toop ( if that's the case ) with the utmost respect and with all appreciation and love. I would be very happy to know that Mr. Toop could help us to preserve the Enterprise in FPGA, just as many of us will surely be.

Let's go for the core !

Regards
ron
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.05. 21:38:13
To do a first approach to the core, I will try to explain what we plan to do.

There are two coders who do great things. They are Gyorgy (Gyurco aka slingshot) and Sorgelig. Both are among the most representative in MiST and MiSTer. Both have two separate Sam Coupé cores implemented.

Calm down, let's be calm. Yes, I said Sam Coupé. But I will explain what all this means. Everyone knows that the Enterprise is a better micro than the Sam Coupé. Enter is a design from 1983, Sam is almost 1989.

Isn't it strange to have the Sam Coupé instead of the Videoton as a base?. The Videoton is similar in software, but not in hardware, which is what it's all about here. We believe that Miles Gordon Technologies must have looked sideways at the Enterprise, because coincidentally, there are many circumstances that make it optimal to take advantage of what has already been done.

This is the Sorgelig's git: https://github.com/sorgelig/SAMCoupe_MIST
This is the gyurco ( slingshot) git: https://github.com/gyurco/SAMCoupe_MIST

Obviously the core of Enteprise once it is ready to implement Nick and Dave is not going to look anything like the original.

The rom is already loading it by ioctl_download to the sdram, paging to 16Kb blocks ... it is not so different ... with the appropriate changes we do not see any impediment to use them as a base on which to implement. It is a good start. From what we see the way of reading the keyboard is very similar to that of AY. About Dave, it's very similar. At The moment we have clear audio records, it will not be very difficult to prototype that chip and the paging based on outs is cpm type.

In a later phase it is a question of supplanting the ASIC of Sam by Nick and SAA by Dave.

It is an initial stage it is about prototyping until the nick is able to start generating and painting video. We have to see how far we can go, since in other cores the parts that were missing until the schemes were obtained or decapped, were based on what was written in emulators.

Feel free to comment and add what arouses your interest or points of view.

Regards
ron

Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.May.06. 22:40:18
Wow - this is very exciting news. :mrgreen:

I guess the hardest bits will be programming the Nick chip's line parameter table. And of course getting cycle exact emulation (but that can always be worked out later).

The official Nick and Dave chip documentation provides a very good start: 
http://ep.homeserver.hu/Dokumentacio/Konyvek/EXOS_2.1_technikal_information/hardware/Nick.html
http://ep.homeserver.hu/Dokumentacio/Konyvek/EXOS_2.1_technikal_information/hardware/Dave.html

And IstanV knows a lot about the undocumented behaviour!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.07. 11:29:17
Thanks dangerman.

These links are extracted from the official Nick (http://enterprise.iko.hu/technical/ET1-3_Nick_Chip_Programmers_Guide.pdf) and Dave (http://enterprise.iko.hu/technical/DAVE_ISSUE5.pdf) documents that we are already managing. Do they have any fixing over the originals?

Yes, of course we want IstvanV advice and collaboration.



Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.May.07. 11:50:12
These documents may also be somewhat interesting:
ELITE (NICK) Rev.E (final) Sheet 1 (http://enterprise.iko.hu/schematics/3006-0000-22_Sheet-1.pdf)
ELITE (NICK) Rev.E (final) Sheet 2 (http://enterprise.iko.hu/schematics/3006-0000-22_Sheet-2.pdf)
ESPRIT (DAVE) Rev.D (final) Sheet 1 (http://enterprise.iko.hu/schematics/3007-000-22_Sheet-1.pdf)
ESPRIT (DAVE) Rev.D (final) Sheet 2 (http://enterprise.iko.hu/schematics/3007-000-22_Sheet-2.pdf)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.07. 12:22:24
Thanks ergoGnomik.

Yes, there are invaluable documents on Zozo's page. I hope that the geniuses on the project could translate all that little boxes on the design.

The sheets seem to be modified on some parts. If they are effectively the latests revisions E and D(the fixed NICK?), maybe they will lead to a good implementation of the chips.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.May.07. 12:49:15
These links are extracted from the official Nick (http://enterprise.iko.hu/technical/ET1-3_Nick_Chip_Programmers_Guide.pdf) and Dave (http://enterprise.iko.hu/technical/DAVE_ISSUE5.pdf) documents that we are already managing. Do they have any fixing over the originals?

Great stuff. Those will probably be the best place to start. I'm not totally sure but I don't believe there are any fixes in the HTML version.

Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Tutus on 2020.May.07. 13:13:49
Greetings to all users and lovers of the Elan Enterprise.
The main objective is to achieve an Enterprise 128 implementation that works on FPGA boards like MiST, MiSTica and SiDi and so that later FPGAs like the MiSTer can be ported.

Hi ron!

We also had such a plan two months ago, but due to lack of money and specialist, we gave it up ...
So, yours is the "track", if we can help you with anything, let me know!
We have a Hungarian Enterprise Club community behind us. You can count on us! :)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.08. 09:04:28
Thank You very much !
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.09. 22:25:55
Hi there, fellows !

We have some progress, much more than we could expect. Our friend rampa069 has not given us time nor to assimilate all that he has already managed to do. Amazing !

Because the FPGA's SDRAM has 24 addressing bits, rampa069 has successfully reduced the Enterprise MMU in a very smart way. First 8 bits (Content of the port pointed to by the two high lines as a bank) +2 bits (The active port (B0, B1, B2, B3)) + 14 low bits of the address bus..., as soon as a Pseudo_NICK can start painting, there are a lot of possibilities that it will start working right away.

So, Kyp is redoing the control signals but since kyp uses a 28MHz master clock,  with clock enables it is more messy. There are a lot of clocks out of combinatorics and that doesn't like the FPGA. The advantage of FPGA implementations is that as milestones are achieved, you can start testing.

Now ROM loads OK, just using a EP128.ROM file at SD's root in where you can concatenate all ROMS you want. It loads from SD at address 0.-

Also the disc controller is working.

[attach=1]
[attach=2]

Surely tonight ramp069 will enable the Git and all the part already converted to EP128 will be deployed. More or less these are the news we have, it seems that everything is going faster than expected.



Best Regards
ron
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.May.10. 05:28:40
Good news! :smt041 :smt038
That was quick!!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.11. 07:30:14
... and pseudo-Nick started painting.
[attachimg=1]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.May.11. 08:20:04
Cool :smt041
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.11. 10:32:14
Some other documents which were not mentioned previously:
http://enterprise.iko.hu/technical/NICK-Old-VDC-ELITE-description.pdf
http://enterprise.iko.hu/technical/NICK-Internal-timing-of-VDC-Elite.pdf
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.11. 10:40:01
Thanks, Zozo. Now they are working more with the timings that these 2 documents describe.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.11. 13:55:11
Another important thing: clocks calculations by IstvanV (https://enterpriseforever.com/programming/what-is-the-number-of-clock-cycles-per-rasterline/msg63481/#msg63481)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.11. 13:59:32
Some scope measurements about Nick-Z80, VRAM access (in Hungarian forum :oops: )
https://enterpriseforever.com/kijelzo/nick/msg32713/#msg32713
https://enterpriseforever.com/kijelzo/nick/msg32717/#msg32717
https://enterpriseforever.com/kijelzo/nick/msg32723/#msg32723
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.11. 15:13:44
Great! Thanks Zozo.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.11. 20:06:44
After the improvements, the pseudo Nick says HELLO! and you already use the EXOS font

[attachimg=1][attachimg=2]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.11. 20:29:49
[attach=1]

@Kyp:

"No solo se ve, está 'procesando' la LPT, leyéndola de la RAM. En esa imagen están las dos bandas del borde superior e inferior, 28 bandas en modo CH128 (cambiando el puntero a donde empieza el texto) y las dos bandas en modo VSYNC para el sincronismo vertical :grin: "

----

"It not only sees, it is 'processing' the LPT, reading it from Ram. In  this image there are the two bands, upper and lower, 28 bands in CH128 mode (modifying the pointer where starts the text) and the two bands on VSYNC mode for the vertical synchronism :grin: "
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kapitany on 2020.May.11. 22:11:54
Will there be a design for a nice case and keyboard, so that in the trails of the Spectrum Next there could be a Nexterprise? :D If the proof of concept is OK, there should be a Kickstarter project for this as well, don't you think so?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.May.12. 10:25:59
That Kickstarter would be sentenced to death. People know what a Commodore 64 or a ZX Spectrum is, but they don't know what an Enterprise 64/128 computer is. People are seldom interested in yet another thing they have no clue about.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.12. 11:27:58
The aim of this project  is to preserve the Enteprise in FPGA. It is time to do it.



We are developing the Enterprise core on the MiST / MiSTica / SiDi platform but with the intention that once it is functional, can be ported to other fpga boards such as the MiSTer or those where it fits. There is no point in kickstarting or crowfounding, in this case all that is useless.

This project is public, open-source, totally independent, non-profit and is done unconditionally for pure fun and learning.

So, preservation. Emulation already takes care of this purpose, but we consider that an implementation on gate arrays can offer a more exact and precise view of the Enteprise, without detracting from everything that already exists, since without it this would not be possible. Anyone can help and contribute to improvement

As soon as we have news we will gladly share them with you.

Thanks for all documentation, maybe we will transfer you some questions about timings and specific things, all in due time.

Thank You
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.12. 11:47:05
Is possible when the development done, create new Nick and Dave chips which can be used for repair dead Enterprise machines?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.12. 12:04:02
Is possible when the development done, create new Nick and Dave chips which can be used for repair dead Enterprise machines?

Knowing the number of logical gates that each custom chip occupies, you could look for a cpld or fpga that has enough capacity and the necessary pins and could be mounted on a socket or an adapter.

What I couldn't tell you right now is how to take advantage of what is already in place, but I pass the question on to colleagues.

And to the question of whether it can, if the implementation actually meets all the requirements that the Enterprise needs, is YES.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.15. 21:23:24
Here I bring you a little video of what is actually happening with this development.

My friend Kyp has some restrictions on his actual FPGA, only 64KB of internal Ram, perfect for Video Ram, but he also needs to put the EXOS Roms there, because he has 4MB of external Ram but no way to put Roms on that space.

A member of the development group has donated Kyp a better FPGA, so on some days we will see more advances. Think that all this work is done on free time.

Kyp:


Details...
I am using the BRAM to share the memory with the CPU and still without timing contention but, just because I have the (EXOS)Rom on the BRAM, I only have 32K of ROM and 32K of VRAM, I have searched which two segments of VRAM the ROM uses to draw on the screen to be able to show some text(still only hardware text mode). And then it can't start... because it needs a pressed key and by now there is no keyboard at all.

Kyp says that the keyboard hardware seems trivial, but to continue he also needs to implement the interrupts.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.16. 11:18:46
Thanks GFlorez !

From this moment on and depending on the time that rampa069 may take, things will start to go faster and then a point will be reached where the debugging and testing phase will enter.

Remember that core's structure and other elements were already implemented and running.

It is a slow and tedious process, since with FPGAs there is no way of knowing what is happening and it becomes difficult.

Anyway, now is when this turns really interesting. Stay Tuned !
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kapitany on 2020.May.19. 10:06:38
Wonderful news! It's nice to see that EXOS can now open graphic channels and display them in windows on the screen, no matter that the graphics mode is a bit glitchy. :) Well done, keep up the good work!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.19. 10:25:04
The graphic modes aren't still implemented.... Is for it that the flashing big letters are shown as 0s and 1s, because the "pseudo Nick" thinks it is hardware text mode...

Now a keyboard and interrupts have to be implemented. Also the memory is not properly managed.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.19. 10:32:29
The graphic modes aren't still implemented....
Palette colors are also not :oops: This is why visible the ERROR at the memory test. It is using the second color pair, and normaly set to black letters, only changed to red when memory error found.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.19. 11:06:07
Great clue! Thanks Zozo, I am going to inform about that.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kapitany on 2020.May.19. 21:39:41
So that's why it's worth to show us status videos more and more frequently, so that Zozo can spot such clues that lead to things that might be debugged for endless hours. :D "Who can see into the soul of the EXOS?" :D
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.May.23. 19:23:47
HI there, good news !!!

[attachimg=1]
[attachimg=2]

Thanks to Kyp !!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Zozosoft on 2020.May.23. 19:43:08
Looks good! :smt038
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.May.23. 20:09:45
Amazing progress!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.23. 21:13:59
Still not totally good interruptions. And no Basic.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Tutus on 2020.May.24. 08:52:57
Still not totally good interruptions. And no Basic.
Great!!! :smt041
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.May.24. 12:45:24
Looks cool :)
And the progress is amazing.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.May.24. 14:19:53
Wow. This is really fast progress. Fantastic!!! :smt041 :smt041
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kapitany on 2020.May.26. 07:42:43
Wow! This is really nice! Right on Commander! :)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: MrPrise on 2020.May.26. 10:58:12
Looks great, keep up the good work! Kyp is on his way here :-) (his account has been created today)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.May.26. 15:27:14
Yes, that way he can make you all a lot of questions directly.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.May.26. 19:10:17
Hello everybody!

I never had an Enterprise so I have little to tell about me and these computers. I knew about them just in publications and lately I have seen gflorez computers in action. I had and still have Spectrums and Amigas.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.May.26. 21:59:24
welcome here, and congratulation for the fast and good result you achieved: -)
I had ENTERPRISE and C64 and i still have ;-)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.August.18. 13:27:39
Kyp is hardly still developing the core. This is his last post:

"The biggest problem the EP has is that many of the things it does with signals are managed in a 'incompatible' way with FPGAs. It has lots of latches and registers that work with clocks coming out from other logic gates and FPGAs don't like that at all."
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Tutus on 2020.August.18. 13:39:04
Kyp is hardly still developing the core. This is his last post:

"The biggest problem the EP has is that many of the things it does with signals are managed in a 'incompatible' way with FPGAs. It has lots of latches and registers that work with clocks coming out from other logic gates and FPGAs don't like that at all."
It is very sad :(
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: elmer on 2020.August.18. 15:31:49
It is very sad :(

Yes, very sad. :(
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.August.18. 15:48:50
You have not understood him. It is hard but he continues.

He only is explaining the difficulties he is finding.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.August.18. 18:07:05
You have not understood him.
I'm sorry to say this, but it is actually you who made Tutus misunderstand. You see, working hard and hardly working are very different things. Working hard means that somebody makes great efforts to achieve the goal. Hardly working means doing not much or barely anything. Yes, hardly and hard can be used as equivalents, but that is not the usual or most common meaning of hardly.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: BruceTanner on 2020.August.18. 18:19:08
Yes, I misunderstood too. Also "This is his last post" I took to mean his last post ever, his final post. "...his latest post" would be better.

I say this just for information, not to criticize, I am in awe at people's ability to use English on this forum :bow: it puts my language skills to shame :oops: :oops: :oops:
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: elmer on 2020.August.18. 19:36:45
I say this just for information, not to criticize, I am in awe at people's ability to use English on this forum :bow: it puts my language skills to shame :oops: :oops: :oops:

I agree, I'm amazed at all of the posts in English from people for whom it is a 2nd or 3rd language. It makes me ashamed of my poor language skills.

I'm really glad to hear that the development is continuing. :-)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: szipucsu on 2020.August.18. 21:04:01
hardly and hard can be used as equivalents
I think they cannot be used as equivalents. But you are right saying "hardly" means "very-very little" or "almost not". As I know "hardly" can have nothing to do with "hard". But correct me if it is not true.
(Hard - hardly are exceptions. A lot of other words like this have similar meanings, e.g. soft - softly or happy-happily.)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.August.18. 22:51:51
Apologies.... You all are right....

When I have received my friend's message I was doing shopping. I was eager for sharing it after so much time without news, so I have put the Spanish text on google and directly to this forum the translation.... My own text also was defective, so I also have some culpability....

Later, still shopping... I have read the answers and I have tried to change the sense of my earlier commentary.... and maybe some of you have been offended.


Yes I wanted to mean "working hard", not "hardly working". Some times on Spanish the order of the adjective is not significant on the sentence, and this is one of these cases: "duro trabajo" and "trabajo duro" is practically the same.

Also, the meaning of "último"("last") is not so definitive as in English, it is only the more recent in a succession of events, not the last of this era, never, the end, etc.

So yes, the development continues. Kyp means that the Enterprise chips will be the harder part to implement and trim, but there is a team behind to support him..

Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.August.19. 10:22:07
/OFF
hardly:
Google Translate (https://translate.google.hu/#view=home&op=translate&sl=auto&tl=hu&text=hardly)
topszótár (https://topszotar.hu/angolmagyar/hardly)
MorphoLogic (http://www.webforditas.hu/szotar.php?S=hardly&l1=en&l2=hu)
/ON
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.September.07. 13:35:35
I've been busy with other things but the project is still alive. Be patient.

I have a question.

ROM boot test doesn't show CPU speed, I think it's because I haven't implemented interrupts yet. I'm right? Well I just wired the VSYNC interrupts directly to the INT signal of the CPU, but I guess it's not correct. I'm not sure about how interrupts work in general. I have read about Dave's registers, but I am not sure how they work. For example, what is connected to INT1 or INT2?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.September.07. 18:37:11
yes, the cpu speed is calculated based on numbers of 1KHz Dave interruts within 1 50Hz Nick interrupt. Dave speed is increasing with the CPU speed.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.September.07. 18:41:55
as i saw Nick interrupt is on int1, and nothing on int2
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.September.12. 11:00:49
as i saw Nick interrupt is on int1, and nothing on int2

It's been a while but I seem to remember that int2 is connected to the network port, so that networked Enterprises can be alerted if another machine is sending data.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.September.12. 11:19:17
Well I just wired the VSYNC interrupts directly to the INT signal of the CPU, but I guess it's not correct. I'm not sure about how interrupts work in general. I have read about Dave's registers, but I am not sure how they work. For example, what is connected to INT1 or INT2?

On the Enterprise, interrupts are connected to the DAVE chip and then DAVE controls the INT signal of the CPU. Interrupts are latched by DAVE so they can get passed to the CPU (eventually) even if they occur when Z80 interrupts are temporarily disabled.

DAVE has 4 sources of interrupts...

1. Variable frequency interrupt - either 50Hz, 1kHz or a variable frequency specified by the tone generator (ie the pitch of sound)
2. An interrupt at 1Hz
3. INT1 - this is connected to the Nick chip interrupt
4. INT2 - I think this is connected to the network port, so you probably don't need to worry about it.

You can find out what interrupts have occurred by reading DAVE register $B4.
You enable/disable the different interrupt sources and clear interrupt latches by writing to DAVE register $B4.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.September.21. 23:25:29
All info about Enter interruptions is very appreciated.
The core is getting a great shape. :-)

See you soon. Regards-.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.October.11. 20:08:02
Its alive!
[attachimg=1] (https://youtu.be/AH6Wm9jSnnI)

It still needs a lot of work, but at least it boots to BASIC :D
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.11. 21:23:23
Nice progress!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.11. 21:34:43
cooooooool !
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.October.11. 23:27:16
Excellent stuff!!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Trefe on 2020.October.12. 12:30:53
Amazing. 0.87MHz NMOS Z80? ;-) Like...
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.12. 13:04:05
Yes... Zozo's routines to calculate the Z80 frequency need correct interrupts. The real clock in the video is 3.5Mhz.

[attachimg=1]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Tutus on 2020.October.12. 13:53:43
This is fantastic! :smt038  Giant! :)
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.October.12. 17:15:12
Only video timings are accurate. CPU timings are far from exact. Z80 is clocked at 3.5 MHz and there is no contention. I'd rather have something that works first and tune-up it later.

I have already done a very accurate implementation of a Sinclair ZX Spectrum. It was very useful to have lots of test programs that check almost every detail of Spectrum's operation. Is there something similar to test the Enterprise?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ergoGnomik on 2020.October.12. 19:40:53
Is there something similar to test the Enterprise?
You may try to ask IstvanV (https://enterpriseforever.com/profile/?u=80) of ep128emu (https://github.com/istvan-v/ep128emu) fame if he had something around those lines during the development of his emulator.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.12. 20:22:46
Another video, loading a Basic listing(still without audio):


[attachimg=2]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.12. 20:31:20
Sorry, this one is loading from TAPE:
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.13. 19:49:21
It's Working.
At the moment is Enterprise 64, looking for wav files to test.

Regards
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.13. 20:18:07
[attachimg=1]
[attachimg=2]
[attachimg=3]
[attachimg=4]

Hurra !!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.13. 20:30:32
Very impressive!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.13. 23:30:35
https://www.twitch.tv/videos/769376277
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.14. 08:34:46
Impressive progress, did i see well an attribute mode picture was started to load also?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.14. 08:56:48
Yes, amazing. Kyp only has implemented  TEXT 40 and GRAPHICS LOWRES 256, necessary for booting EXOS, show the flashing letters and start Basic, but it seems that it can also show HIRES, TEXT 80 and other colour modes....

Attribute? I think still not. But Ron once loaded part of a screen with a lot of colours... It can be.

Probably you have noticed that only 8 colours can be seen on the 256 colours demo... This is not a defect of the core, but from the ZXUNO FPGA device, intended to manage the Spectrum core. Soon the team will port the Enterprise core to other more powerful FPGAs.

Other aspect was that a lot of programs failed to load, but I think that it was due to lack of Ram space. Kyp says he will add more on the next update.

As a proof of concept I think it is very impressive.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.October.14. 09:48:09
Video modes 000 (VSYNC), 001 (PIXEL, partially) and 100 (CH128, including ALTIND0 and ALTIND1) and the four color modes are implemented. The FIXBIAS registry is not implemented yet.

The problem with colors in 256 color mode is not a limitation of the ZX-Uno board. It must be a bug in the implementation.

My ZX-Uno board has 512K of SRAM (can be expanded up to 2MB). 64K are reserved for ROM. The rest can be used as RAM easily.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.14. 13:26:07
Other aspect was that a lot of programs failed to load, but I think that it was due to lack of Ram space. Kyp says he will add more on the next update.
Yes, most programs are not running on EP64, old Speccy ports because they are using fix segments (F8-FB) except Zozo's conversions, most of newer ones need more memory.
Almost all programs which runs on EP64 (http://ep128.hu/Ep_Games/Games_Ep64_eng.htm) lister here except those which run, but slowly.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.October.14. 18:10:28
ZX-Uno board has 512K of SRAM but I need to reserve 64K for ROM leaving just 448K free. It is possible to have 448K of RAM? Or must be a power of two? BTW, I already have 128K of RAM :D

[attachimg=1]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.15. 09:27:43
Yes, you can define any of x16KB of RAM which is greater than 64KB
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.15. 12:38:32
Enteprise core is being deployed on Altera boards, such MiSTer, MiST, MiST
Now to implement Dave and more things....

https://www.twitch.tv/videos/770392152

Bye !
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.16. 22:47:53
More advances, more stuff:

[attachimg=2]
[attachimg=3]
[attachimg=4]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.17. 06:57:26
WOW!!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.17. 18:00:25
I think it is a dream only ;-)
It seems Nick is close to perfect, and there is extra memory.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.17. 20:09:53
is there any tool to convert TAP to WAV in order to load via Audio ?

If not, we need TAP format information.

Thanks very much. ron.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.17. 20:49:24
Here you find two older tools as well, EPTE and TAPir, but better solution is EP128emu's TAPEEDIT:

http://www.ep128.hu/Ep_Emulator_eng.htm
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.17. 20:49:47
tapeedit is part of EP128emu, you can try that, i hope it can generate WAV files also.
As i remember EPTE (http://www.ep128.hu/Emu/EPTE.RAR)  can create WAV file, or at least it creates WAV file during tap conversion into a folder.
As i see TAPir (http://www.ep128.hu/Emu/TAPir.rar) can create WAV files.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.19. 18:58:55
All right. Thank You. Let's go with more advances: Attribute Mode

[attachimg=1]
[attachimg=2]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: dangerman on 2020.October.19. 22:35:20
Amazing!!!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kapitany on 2020.October.20. 16:14:02
Amazing! I always used TAPir to convert programs to WAV format. I have converted a bunch of games to WAV, maybe you can use them for something... https://www.dropbox.com/s/lh80oycdb5s1vx8/EP_GAMES.zip?dl=0
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.20. 17:46:02
Some more WAVs & mp3s converted by me earlier (didn't test all of them, some might be faulty):

https://mega.nz/file/RNMV2IIY#TlU7_QJVZ7kj84PoU3_BfNmqqvuH0CyefWTXpq3nLIU
https://mega.nz/file/wBEBSSYD#7-gVJedwwwBg5070bbrLt3lindm1xAuaG_gWjAWYkAM
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Kyp on 2020.October.24. 18:38:05
I have been loading some games... Thank you for the WAV files :)

(https://i.postimg.cc/R3BLRrk0/01-bruce-lee.jpg) (https://postimg.cc/R3BLRrk0) (https://i.postimg.cc/qhBcPsMV/02-bruce-lee.jpg) (https://postimg.cc/qhBcPsMV) Bruce Lee does not work :(

(https://i.postimg.cc/2bHdr1Vq/01-highway-encounter.jpg) (https://postimg.cc/2bHdr1Vq) (https://i.postimg.cc/23KdtLsM/02-highway-encounter.jpg) (https://postimg.cc/23KdtLsM)

(https://i.postimg.cc/QHKgZxst/01-jetpac.jpg) (https://postimg.cc/QHKgZxst) (https://i.postimg.cc/KKDrpqbD/02-jetpac.jpg) (https://postimg.cc/KKDrpqbD) (https://i.postimg.cc/7CwSz3zG/03-jetpac.jpg) (https://postimg.cc/7CwSz3zG)

(https://i.postimg.cc/HrGwYDst/01-nodes-of-yesod.jpg) (https://postimg.cc/HrGwYDst) (https://i.postimg.cc/Yj9f8zsQ/02-nodes-of-yesod.jpg) (https://postimg.cc/Yj9f8zsQ) (https://i.postimg.cc/Mc5Vmn0s/03-nodes-of-yesod.jpg) (https://postimg.cc/Mc5Vmn0s)

(https://i.postimg.cc/wR7Xv9mw/01-saboteur.jpg) (https://postimg.cc/wR7Xv9mw) (https://i.postimg.cc/Yv11jnvB/02-saboteur.jpg) (https://postimg.cc/Yv11jnvB)

There are some graphics glitches but overall it looks good
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.25. 00:47:07
Yes yes YES ! Many of the games loads and playable !!!
In MiSTer fpga we're still fighting to normalize the audio loading, it's still buggy.

In any case, the core itself is already a reality, it is true that there is still a long way to go and that there are many difficulties to overcome, but this is very emotional because a lot of love is being given so that the Enteprise will remain well preserved.

[attach=1]
[attach=2]
[attach=3]
[attach=4]
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Dr.OG on 2020.October.25. 05:09:43
AVESOME!!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: geco on 2020.October.25. 07:11:19
Incredible effort !!!
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: Trefe on 2020.October.26. 19:15:07
Amazing. :shock:  Does this work for SIDI?
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: gflorez on 2020.October.26. 20:58:57
Yes, Mist, Sidi, Mister, etc. The development is being done on a ZXUNO, with a smaller FPGA, and then converted to the other ones.
Title: Re: Enterprise Deployment Attempt Over FPGA.
Post by: ron on 2020.October.27. 07:17:26
There is a small hurdle to overcome in MiST. The MiST needs Quartus 13 to synthesize the cores, and instead both MiSTer and SiDi use the Quartus 17 versions. Our preferred manufacturer (manuferhi.com) will port to MiST. Actually I would love for the MiST port to be a success.

Remember that SiDi carries a Cyclone IV and the MiST a Cyclone III, yes, both have similar characteristics, memory, cells, but it is much easier to port to SiDi right now than to MiST.

Regarding the state of the core right now. You have to finish the Nick and start preparing the Dave. Later, depending on how the BUS can be implemented, it is necessary to think about either the disk controller or the SD-Card.
It shouldn't be a problem to equip the core with up to 4 MB of ram. Right now the audio upload works very well in ZXUNO but in MiSTer it is giving some problems due to the DAC converter.

We will keep you informed, thanks for all the support.