Will there be a design for a nice case and keyboard, so that in the trails of the Spectrum Next there could be a Nexterprise? If the proof of concept is OK, there should be a Kickstarter project for this as well, don't you think so?

The aim of this project  is to preserve the Enteprise in FPGA. It is time to do it.



We are developing the Enterprise core on the MiST / MiSTica / SiDi platform but with the intention that once it is functional, can be ported to other fpga boards such as the MiSTer or those where it fits. There is no point in kickstarting or crowfounding, in this case all that is useless.

This project is public, open-source, totally independent, non-profit and is done unconditionally for pure fun and learning.

So, preservation. Emulation already takes care of this purpose, but we consider that an implementation on gate arrays can offer a more exact and precise view of the Enteprise, without detracting from everything that already exists, since without it this would not be possible. Anyone can help and contribute to improvement

As soon as we have news we will gladly share them with you.

Thanks for all documentation, maybe we will transfer you some questions about timings and specific things, all in due time.

Thank You

Is possible when the development done, create new Nick and Dave chips which can be used for repair dead Enterprise machines?

Knowing the number of logical gates that each custom chip occupies, you could look for a cpld or fpga that has enough capacity and the necessary pins and could be mounted on a socket or an adapter.

What I couldn't tell you right now is how to take advantage of what is already in place, but I pass the question on to colleagues.

And to the question of whether it can, if the implementation actually meets all the requirements that the Enterprise needs, is YES.

Thanks GFlorez !

From this moment on and depending on the time that rampa069 may take, things will start to go faster and then a point will be reached where the debugging and testing phase will enter.

Remember that core's structure and other elements were already implemented and running.

It is a slow and tedious process, since with FPGAs there is no way of knowing what is happening and it becomes difficult.

Anyway, now is when this turns really interesting. Stay Tuned !

The graphic modes aren't still implemented.... Is for it that the flashing big letters are shown as 0s and 1s, because the "pseudo Nick" thinks it is hardware text mode...

Now a keyboard and interrupts have to be implemented. Also the memory is not properly managed.

Great clue! Thanks Zozo, I am going to inform about that.

HI there, good news !!!

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Thanks to Kyp !!!

Amazing progress!