I already checked your sources, and the asynchronous clocks of NIC and the CPU are indeed a problem, but not unsolvable.
The original machine also shares the video RAM page (Dave generates the WAIT_N signal to the CPU - I see it's not implemented (yet), but not a big problem, except for cycle-accuracy).
The 4 MHz Z80 expects the RAM speed (without wait states) at most 2.6 MHz rate (M1 cycle is 1,5 cycles long), so it's no problem for the SDRAM controller.
Nick (should) not use a bigger rate also (as the original DRAMs are not faster). I didn't check the details of your Nick implementation yet, but if it requires the data available after the address setup in 1-2 master cycles, then it should be changed (the displaying pipeline will be longer, but also more faithful to the original). This one also a common problem with lot of cores, while the time between the address setups can be 8-16 pixel clock cycles, the data is expected to be returned in 1 cycle. It's clearly for BRAM, and not really how the original hardware worked.
Finally the Amstad CPC uses a similar display access rate, and it has no problem with the SDRAM controller @64MHz.