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Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 46649 times)

Offline gyurco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #255 on: 2022.November.12. 15:30:11 »
I already checked your sources, and the asynchronous clocks of NIC and the CPU are indeed a problem, but not unsolvable.
The original machine also shares the video RAM page (Dave generates the WAIT_N signal to the CPU - I see it's not implemented (yet), but not a big problem, except for cycle-accuracy).

The 4 MHz Z80 expects the RAM speed (without wait states) at most 2.6 MHz rate (M1 cycle is 1,5 cycles long), so it's no problem for the SDRAM controller.
Nick (should) not use a bigger rate also (as the original DRAMs are not faster). I didn't check the details of your Nick implementation yet, but if it requires the data available after the address setup in 1-2 master cycles, then it should be changed (the displaying pipeline will be longer, but also more faithful to the original). This one also a common problem with lot of cores, while the time between the address setups can be 8-16 pixel clock cycles, the data is expected to be returned in 1 cycle. It's clearly for BRAM, and not really how the original hardware worked.

Finally the Amstad CPC uses a similar display access rate, and it has no problem with the SDRAM controller @64MHz.
« Last Edit: 2022.November.12. 16:05:18 by gyurco »

Offline gyurco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #256 on: 2022.November.12. 16:36:10 »
From the schematics of the Dave chip, it looks like the WAIT_N generator only uses the port BF(?), and doesn't consider if it's VRAM page access or not. Is it true that the CPU throttling is applied to all RAM pages on the original machine?

BTW, it's interesting they choose a design with asynchronous CPU and video clocks. Even the Amiga was designed with synchronous clocks, as making them async can give serious headaches with synchronizing and timing checks (even today, with FPGA designs). Maybe it was one of the reasons why the machine was delayed? It would be more simple if they simply choose a 8MHz pixel clock (16 MHz master clock for the Nick).

Upd.: Seems I was wrong, and the design is even more complicated than I first anticipated: while WAIT_N is generated by Dave, the CPU clock itself is generated by Nick, which can simply disable it (hold at a level - similarly to ZX Spectrum) while it wants to access the VRAM.
« Last Edit: 2022.November.12. 17:42:54 by gyurco »

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #257 on: 2022.November.14. 15:31:26 »
An horizontal line of about 63.7us is divided in 57 columns of 1117ns. A column takes 16 clocks. Nick reads two times in the first 10 clocks, and CPU is allowed to access memory in the last 6 clocks.

My Nick implementation put addresses during all 5 clocks and reads at the negedge of the last one.

Dave wait states are independent of memory contention, I think is safe to ignore it at least for now. As you said, contention is similar to Spectrum, holding Z80's clock.

AFAIK only shared video memory is contended.

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #258 on: 2022.November.14. 16:54:51 »
AFAIK only shared video memory is contended.
Yes, only Video RAM is contended, others are not.

Offline gyurco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #259 on: 2022.November.14. 18:41:18 »
Thanks for confirming.
As I suspected, the SDRAM has no problem with serving both the CPU and Nick (even without contention):
https://ibb.co/mvkLxJc
https://ibb.co/8YfsTpQ

Now it's time to learn about the machine :)
(My friend from elementary school had one, but I only saw playing Last Ninja II).

@Kyp: When I'll complete the port, I'll push my changes to your repo in a separate branch if it's OK to you. Then merging with master can be decided later on.

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #260 on: 2022.November.14. 22:04:14 »
What a wonderful post !
Sounds a bell !
Thanks a lot.

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #261 on: 2022.November.14. 23:36:39 »
it does not synthesize. Even with latest MiST modules
it takes more than 20 minutes, I have stopped , isn't it too much ?
Using Q13.

Regards

Offline gyurco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #262 on: 2022.November.14. 23:47:24 »
It's a very small core, synthesizes in less than a minute:


Fitter Status   Successful - Mon Nov 14 21:11:22 2022
Quartus II 64-Bit Version   13.1.4 Build 182 03/12/2014 SJ Web Edition
Revision Name   enterprise
Top-level Entity Name   enterprise_mist
Family   Cyclone III
Device   EP3C25E144C8
Timing Models   Final
Total logic elements   5,966 / 24,624 ( 24 % )
Total combinational functions   5,279 / 24,624 ( 21 % )
Dedicated logic registers   2,345 / 24,624 ( 10 % )
Total registers   2404
Total pins   72 / 83 ( 87 % )
Total virtual pins   0
Total memory bits   43,008 / 608,256 ( 7 % )
Embedded Multiplier 9-bit elements   9 / 132 ( 7 % )
Total PLLs   1 / 4 ( 25 % )


Do you have Quartus 13 updates installed? The latest is 13.1.4.
Also I noticed that on very new Linux distros, the fitter simply hangs forever.

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #263 on: 2022.November.16. 17:42:28 »
Please, here are first testing versions.
Feedback is very appreciated.

Enjoy the Enteprise on the MiST. Thanks to Gyurco.
Regards.

* Pack_enter_mistisidi_RW.zip

Offline ron

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #264 on: 2022.November.25. 14:15:38 »
http://www.retrowiki.es/viewtopic.php?f=106&t=200038931



For all the friends of Enteprise, next Sunday we will broadcast a live show in which we will present a demonstration of Zozo's new EXDOS 3.0.
Running on real Enteprise hardware and several FPGA boards.

19:30 CET: https://www.twitch.tv/retrocrypta

Offline gflorez

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #265 on: 2022.November.25. 15:01:41 »
(Sorry, I have explained Ron that Zozo is working on the SF3 driver and Bruce Tanner on EXDOS3.0)

Offline Zozosoft

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #266 on: 2022.November.25. 15:31:34 »
(Sorry, I have explained Ron that Zozo is working on the SF3 driver and Bruce Tanner on EXDOS3.0)
Yes, most of work on EXDOS 3 done by Bruce. But now my previous EXDOS fixes and enhancements are officially included in the code.