how do yo load this on the ep?

There are more method, i used the BASIC CODE command to insert small binary code, both file will give the same result, 1st was saved as text, 2nd in tokenized format.

https://www.twitch.tv/retrocrypta
22:00 CET

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Yesterday i could not attend on the live show, I did not see the short notice

Congratulation Rampa, Dave sounded great in the video, Fred was perfect, as i see sometimes still only 2 channels are initialized for digi play

I was surprised on MODPLAY, because the screen were blank, at left bottom were there screen of real EP?
The screen should be in text mode, and display mod specific stuff.

 The 17bits PN can be used on the a,b and c channels. but i dont understand how its done... only swapping the pn7 and pn17 on the noise channel affects the other channels? and how the 9,11 and 13 bit PN are selected? on the noise channel?

Here you can find an extended Dave documentation with IstvánV's extra information, unfortunately it is hungarian, but i hope google translate will give a readable result:
http://www.ep128.hu/Ep_Konyv/Exos.htm#240

as i see:
7 bit PN (selected on tone channel) can be changed to 17/15/11/9 bit PN (specified on port 0a6h)
and now i understand why 7 bit PN selected on a tone channel and setting 10h to 0a6h gives noise, because noise channel is a 17 bit PN at 31KHz this generate pseudo white noise, and by this setting we set 17 bit PN to the tone channel, and it's frequency can be changed, not fix like on noise channel.
4,5 bit PN's are valid only on tone channels.
if bit 4 of 0a6h is not set then tone channels uses the 7bit PN, and noise channel uses the 17/15/11/9 bit PN based on bit3 and bit2 setting of 0a6h, if bit4 is set on 0a6h then tone channels uses the 17/15/11/9 bit PN based on bit3 and bit2 setting of 0a6h and in this case it's clock will be 250KHz and noise channel uses 7 bit PN on the noise channel clock (31,25 kHz) or selected tone channel clock by bit1 and bit0 of 0a6h.

Length of PN series: 2^N-1 (it can not be 0, it would cause forever loop with 0 (0 XOR 0 = 0))

the first load, in the records screen. only two channels. after the ingame, the records screen has the 4 channels.....
may be the problem is not in the audio?

I got 2 ideas:
1st z80 timing is not perfect, and this cause sometimes we have 4 channels ,and sometimes 2, because the Dave initialization routine uses z80 instructions in wait loop.
2nd initialization routine resets the oscillators by ld a,07h out (0a7h), a (to zero phase and output state) and this does not happens on FPGA.
But i think it is not a major issue, since sometimes it is good, and sometimes it is not. Do we have a sequence? ex every 2nd is good? Or is it total random?

I got 2 ideas:
1st z80 timing is not perfect, and this cause sometimes we have 4 channels ,and sometimes 2, because the Dave initialization routine uses z80 instructions in wait loop.
2nd initialization routine resets the oscillators by ld a,07h out (0a7h), a (to zero phase and output state) and this does not happens on FPGA.
But i think it is not a major issue, since sometimes it is good, and sometimes it is not. Do we have a sequence? ex every 2nd is good? Or is it total random?

on reset now, i am writting 07h to 0a7h.  the pattern has changed a bit.

after load : 4 channels.
records screen: 2 channels (an atmosferic pad and the bass)
ingame OK
record screen: 4 channels.

 about the sound... i'm going to wait for bricky showing the bottom part of the screen (may be related) as it is the only program with random channel problems.


 I started today with the FD controller. all seem ok, but i'm getting "controller not ready" looking at the fdc chip all seems ok, but 1 bit ......

 Seems i'm not replying on time to the DRQ request.

 Somebody know the exact contents (input and output) of the 0x18 status port?

Thanks in advance.

Do you also simulated the shadow of I/O ports?
10-13H mirrored at 14-17H, and also used by EXDOS.

If you using EXDOS 1.4, theres is my WD check routine at the start, testing register mirrorings for WD presence. Original EXDOS freeze without WD. Then I added WD check, and the new Controller not ready error, then EXDOS 1.4 can be used without floppy hardware, for example SD only system.

This is my test routine:

Code: ZiLOG Z80 Assembler

1. WDCHECK:        LD A,55H
2.                         OUT (11H),A
3.                         LD A,0AAH
4.                         OUT (12H),A
5.                         PUSH BC
6.                         PUSH BC
7.                         POP BC
8.                         POP BC
9.                         IN A,(15H)
10.                         CP 55H
11.                         RET NZ
12.                         IN A,(16H)
13.                         CP 0AAH
14.                         RET NZ
15.                         LD A,0AAH
16.                         OUT (11H),A
17.                         LD A,55H
18.                         OUT (12H),A
19.                         PUSH BC
20.                         PUSH BC
21.                         POP BC
22.                         POP BC
23.                         IN A,(15H)
24.                         CP 0AAH
25.                         RET NZ
26.                         IN A,(16H)
27.                         CP 55H
28.                         RET

yes, mirroring is implemented, a for loop in basic, shows the same values at startup as the real hardware except for port 0x10 (and mirrored port) the real ep has a 0x00 and the fpga controller a 0x04

Also what the "controller not ready " condition really is?