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Author Topic: Enterprise Deployment Attempt Over FPGA. (Read 54983 times)

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #165 on: 2022.February.10. 12:31:36 »
I mean it is a general colour assignment problem somewhere, because colour 16 mode also contains "bad" colours, and why i think it effects only Bias, because i did not see any colour problem in 4 colour mode. Please try BIAS.BAS on FPGA EP and in EP128emu, and compare the output, you can change the bias value by space.

Probably i misunderstood the colour assignment in your last 2 rows, but it seems to be strange for me.
Bitmap attribute selection is perfect, and if bit3 of palette index is 0 also, then the colour is chosen from the defined colours 0-7 in the LPB (line parameter block = acutally read LPT line), but if bit3 set then colour index bits[2:0] should be chosen from $80 specified palette.
ex:
lpb colours: 0,1,2,3,4,5,6,7
bias: HW value: 1fh, exos value: 0f8h
bitmap data: 10000001b
attr data: 0f1h

result:
background colour is chosen from bias, because bit7 is set, and colour is 0ffh (white) = 0f8h + 07h
foreground colour is chosen from LPB because b3 is 0, and colour is 01h (red)

result on screen: rwwwwwwr

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #166 on: 2022.February.10. 13:24:09 »
background colour is chosen from bias, because bit7 is set, and colour is 0ffh (white) = 0f8h + 07h
¿BIAS value is added to colour value or replaces bits in colour value?

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #167 on: 2022.February.10. 14:12:43 »
¿BIAS value is added to colour value or replaces bits in colour value?

it works on both way, because if bias 11h is set to 80h port then our bias palette will be 88h-8fh, so if colour 0bh set for a pixel then it will get 88h or 03h = 88h + 03h = 8bh colour.

HW bias X ---> 8 * X gives the bias start colour, so if you replace the colour bits, it gives the same result, because last bit7-bit3 is bias specified palette for colour 8-15, and b2-b0 is the colour selected from bias.

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #168 on: 2022.February.10. 15:04:20 »
Perhaps I have misunderstood how bias works. This is how I think bias works:

Col0   00.000.000  Black
Col1   00.000.100  Dark Blue
Col2   00.000.001  Dark Red
Col3   00.000.101  Dark Magenta
Col4   00.000.010  Dark Green
Col5   00.000.110  Dark Cyan
Col6   00.000.101  Dark Yellow
Col7   00.000.111  Dark White
       ^^_^^^____  these bits were be replaced by bias


if BIAS = 11111

Col08  11.111.000  Bluish Gray
Col09  11.111.100  Bright Blue
Col10  11.111.001  Bright Red
Col11  11.111.101  Bright Magenta
Col12  11.111.010  Bright Green
Col13  11.111.110  Bright Cyan
Col14  11.111.101  Bright Yellow
Col15  11.111.111  Bright White


And it is independent of video mode or colour mode.
It is right?

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #169 on: 2022.February.10. 15:24:42 »
I think we found the mistake:
if BIAS is 00h
Col8   00.000.000  Black
Col9   00.000.001  Dark Red
Cola   00.000.010  Dark Green
Colb   00.000.011  Dark Yellow
Colc   00.000.100  Dark Blue
Cold   00.000.101  Dark Purple
Cole   00.000.110  Dark Cyan
Colf   00.000.111  Dark White

if BIAS = 1fh

Col8  11.111.000  Bluish Gray
Col9   11.111.001  Bright Red
Cola   11.111.010  Bright Green
Colb   11.111.011  Bright Yellow
Colc   11.111.100  Bright Blue
Cold   11.111.101  Bright Purple
Cole   11.111.110  Bright Cyan
Colf   11.111.111  Bright White

So bias was properly set up, just after the colour assignment were mixed a bit with colour index.
Yes the bias is mode independent.

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #170 on: 2022.February.10. 15:49:26 »
about interrupts:

Interrupts are controlled by 0b4h register, that sets up which interrupts are enabled.
write:
bit0 - enable Dave defined interrupts (50Hz/1Khz/frequency of tone generator 0 or 1)
bit1 - resets Dave interrupt request flag (if interrupt occurs, interrupt flag is becomes active, it has to reset "manually")
bit2 - enable 1Hz interrupt
bit3 - resets 1Hz interrupt request flag (if interrupt occurs, interrupt flag is becomes active, it has to reset "manually")
bit4 - enable Nick interrupt (video interrupt)
bit5 - resets Nick interrupt request flag (if interrupt occurs, interrupt flag is becomes active, it has to reset "manually")
bit6 - enable INT2 - it is not used, i think it was for future implementation
bit7 - resets INT2 - it is not used, i think it was for future implementation

read:
bit0 - Dave defined interrupts flip/flop(50Hz/1Khz/frequency of tone generator 0 or 1)
bit1 - gives back Dave interrupt status flag (if interrupt occured 1, if not 0 it remains active until it is not reseted by writing bit1 to port 0b4h, and iterrepupt generating until reset)
bit2 - interrupt flip/flop
bit3 - gives back 1Hz interrupt status flag (if interrupt occured 1, if not 0 it remains active until it is not reseted by writing bit3 to port 0b4h, and iterrepupt generating until reset)
bit4 - it contains the value of VINT flag of avtual LPB
bit5 - gives back Nick interrupt status flag (if interrupt occured 1, if not 0, it remains active until it is not reseted by writing bit5 to port 0b4h, and iterrepupt generating until reset)
bit6 - INT2 - it is not used, i think it was for future implementation
bit7 - gives back INT2 - it is not used, i think it was for future implementation

bit0 and bit2 flip/flop are changes when "interrupt time is reached" ex for 1 Hz interrupt it changes in each sec from 0 to 1 and from 1 to 0.
bit1 changes to 1 (interrupt occurs) , if bit0 is changed, and remains in 1 until it is not cleared by setting bit1 of 0b4h port
bit3 changes to 1 (interrupt occurs) , if bit2 is changed, and remains in 1 until it is not cleared by setting bit1 of 0b4h port
bit4 contains the VINT (video interrupt) flag of actually read LPB
bit5 changes to one if LPT pointer starts to read next LPB after LPB which contained VINT flag
This means that if we want to place more working interrupts into LPT, after each LPB contains VINT need to insert an LPB without VINT to activate that place for interrupt.

Standard EXOS LPT with 1 video interrupts, Int occurs when Nick starts to read content of line BAD0

>B900  F7 08 0B 73 B8 FE E9 01 00 36 00 49 FF 24 2D 36
>B910  F7 08 0B 73 C5 E0 E9 01 00 92 00 49 FF 24 2D 36
>B920  F7 08 0B 73 5D E4 E9 01 00 92 00 49 FF 24 2D 36
>B930  F7 08 0B 73 35 E4 E9 01 00 92 00 49 FF 24 2D 36
>B940  F7 08 0B 73 0D E4 E9 01 00 92 00 49 FF 24 2D 36
>B950  F7 08 0B 73 E5 E3 E9 01 00 92 00 49 FF 24 2D 36
>B960  F7 08 0B 73 ED E0 E9 01 00 92 00 49 FF 24 2D 36
>B970  F7 08 0B 73 15 E1 E9 01 00 92 00 49 FF 24 2D 36
>B980  F7 08 0B 73 3D E1 E9 01 00 92 00 49 FF 24 2D 36
>B990  F7 08 0B 73 65 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9A0  F7 08 0B 73 8D E1 E9 01 00 92 00 49 FF 24 2D 36
>B9B0  F7 08 0B 73 B5 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9C0  F7 08 0B 73 DD E1 E9 01 00 92 00 49 FF 24 2D 36
>B9D0  F7 08 0B 73 05 E2 E9 01 00 92 00 49 FF 24 2D 36
>B9E0  F7 08 0B 73 2D E2 E9 01 00 92 00 49 FF 24 2D 36
>B9F0  F7 08 0B 73 55 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA00  F7 08 0B 73 7D E2 E9 01 00 92 00 49 FF 24 2D 36
>BA10  F7 08 0B 73 A5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA20  F7 08 0B 73 CD E2 E9 01 00 92 00 49 FF 24 2D 36
>BA30  F7 08 0B 73 F5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA40  F7 08 0B 73 1D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA50  F7 08 0B 73 45 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA60  F7 08 0B 73 6D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA70  F7 08 0B 73 95 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA80  F7 08 0B 73 BD E3 E9 01 00 92 00 49 FF 24 2D 36
>BA90  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAA0  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAB0  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAC0  F2 92 3F 00 00 00 00 00 00 00 00 00 00 00 00 00  --- vint
>BAD0  FD 10 3F 00 00 00 00 00 00 00 00 00 00 00 00 00
>BAE0  FE 10 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BAF0  FC 10 3F 1C 00 00 00 00 00 00 00 00 00 00 00 00
>BB00  F0 12 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BB10  EB 13 3F 00 00 00 00 00 00 00 00 00 00 00 00 00


Modified EXOS LPT with 3 interrupts, Int occur when Nick starts to read BA90, and BAB0, and BAD0

>B910  F7 08 0B 73 C5 E0 E9 01 00 92 00 49 FF 24 2D 36
>B900  F7 08 0B 73 B8 FE E9 01 00 36 00 49 FF 24 2D 36
>B920  F7 08 0B 73 5D E4 E9 01 00 92 00 49 FF 24 2D 36
>B930  F7 08 0B 73 35 E4 E9 01 00 92 00 49 FF 24 2D 36
>B940  F7 08 0B 73 0D E4 E9 01 00 92 00 49 FF 24 2D 36
>B950  F7 08 0B 73 E5 E3 E9 01 00 92 00 49 FF 24 2D 36
>B960  F7 08 0B 73 ED E0 E9 01 00 92 00 49 FF 24 2D 36
>B970  F7 08 0B 73 15 E1 E9 01 00 92 00 49 FF 24 2D 36
>B980  F7 08 0B 73 3D E1 E9 01 00 92 00 49 FF 24 2D 36
>B990  F7 08 0B 73 65 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9A0  F7 08 0B 73 8D E1 E9 01 00 92 00 49 FF 24 2D 36
>B9B0  F7 08 0B 73 B5 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9C0  F7 08 0B 73 DD E1 E9 01 00 92 00 49 FF 24 2D 36
>B9D0  F7 08 0B 73 05 E2 E9 01 00 92 00 49 FF 24 2D 36
>B9E0  F7 08 0B 73 2D E2 E9 01 00 92 00 49 FF 24 2D 36
>B9F0  F7 08 0B 73 55 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA00  F7 08 0B 73 7D E2 E9 01 00 92 00 49 FF 24 2D 36
>BA10  F7 08 0B 73 A5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA20  F7 08 0B 73 CD E2 E9 01 00 92 00 49 FF 24 2D 36
>BA30  F7 08 0B 73 F5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA40  F7 08 0B 73 1D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA50  F7 08 0B 73 45 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA60  F7 08 0B 73 6D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA70  F7 08 0B 73 95 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA80  F7 88 0B 73 BD E3 E9 01 00 92 00 49 FF 24 2D 36  --- vint
>BA90  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAA0  F7 88 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36  --- vint
>BAB0  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAC0  F2 92 3F 00 00 00 00 00 00 00 00 00 00 00 00 00  --- vint
>BAD0  FD 10 3F 00 00 00 00 00 00 00 00 00 00 00 00 00
>BAE0  FE 10 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BAF0  FC 10 3F 1C 00 00 00 00 00 00 00 00 00 00 00 00
>BB00  F0 12 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BB10  EB 13 3F 00 00 00 00 00 00 00 00 00 00 00 00 00

Modified EXOS LPT, it contains VINT in 3 lines, but only 1 interrupt will occur when Nick starts to read content of BAD0

>B900  F7 08 0B 73 B8 FE E9 01 00 36 00 49 FF 24 2D 36
>B910  F7 08 0B 73 C5 E0 E9 01 00 92 00 49 FF 24 2D 36
>B920  F7 08 0B 73 5D E4 E9 01 00 92 00 49 FF 24 2D 36
>B930  F7 08 0B 73 35 E4 E9 01 00 92 00 49 FF 24 2D 36
>B940  F7 08 0B 73 0D E4 E9 01 00 92 00 49 FF 24 2D 36
>B950  F7 08 0B 73 E5 E3 E9 01 00 92 00 49 FF 24 2D 36
>B960  F7 08 0B 73 ED E0 E9 01 00 92 00 49 FF 24 2D 36
>B970  F7 08 0B 73 15 E1 E9 01 00 92 00 49 FF 24 2D 36
>B980  F7 08 0B 73 3D E1 E9 01 00 92 00 49 FF 24 2D 36
>B990  F7 08 0B 73 65 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9A0  F7 08 0B 73 8D E1 E9 01 00 92 00 49 FF 24 2D 36
>B9B0  F7 08 0B 73 B5 E1 E9 01 00 92 00 49 FF 24 2D 36
>B9C0  F7 08 0B 73 DD E1 E9 01 00 92 00 49 FF 24 2D 36
>B9D0  F7 08 0B 73 05 E2 E9 01 00 92 00 49 FF 24 2D 36
>B9E0  F7 08 0B 73 2D E2 E9 01 00 92 00 49 FF 24 2D 36
>B9F0  F7 08 0B 73 55 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA00  F7 08 0B 73 7D E2 E9 01 00 92 00 49 FF 24 2D 36
>BA10  F7 08 0B 73 A5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA20  F7 08 0B 73 CD E2 E9 01 00 92 00 49 FF 24 2D 36
>BA30  F7 08 0B 73 F5 E2 E9 01 00 92 00 49 FF 24 2D 36
>BA40  F7 08 0B 73 1D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA50  F7 08 0B 73 45 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA60  F7 08 0B 73 6D E3 E9 01 00 92 00 49 FF 24 2D 36
>BA70  F7 08 0B 73 95 E3 E9 01 00 92 00 49 FF 24 2D 36
>BA80  F7 08 0B 73 BD E3 E9 01 00 92 00 49 FF 24 2D 36
>BA90  F7 08 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36
>BAA0  F7 88 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36  --- vint
>BAB0  F7 88 3F 74 B8 FE E9 01 00 92 00 49 FF 24 2D 36  --- vint
>BAC0  F2 92 3F 00 00 00 00 00 00 00 00 00 00 00 00 00  --- vint
>BAD0  FD 10 3F 00 00 00 00 00 00 00 00 00 00 00 00 00
>BAE0  FE 10 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BAF0  FC 10 3F 1C 00 00 00 00 00 00 00 00 00 00 00 00
>BB00  F0 12 06 3F 00 00 00 00 00 00 00 00 00 00 00 00
>BB10  EB 13 3F 00 00 00 00 00 00 00 00 00 00 00 00 00
« Last Edit: 2022.February.10. 15:55:58 by geco »

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #171 on: 2022.February.10. 17:09:18 »
what i forgot to write:
bit0,2,4 are updated even if the corresponding interrupts are disabled.

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #172 on: 2022.February.10. 18:39:08 »
Regarding bias...

I don't understand.

I said Col2 = 00.000.001 = Dark Red so, with bias h00, ColA should be the same = 00.000.001 = Dark Red, is not it?
Why do you say that ColA = 00.000.010 = Dark Green ?

And the same with bias = h1F, ColA = 11.111.010 = Bright Green ?
I understand that 11.1111.xxx is bias but why xx.xxx.001 turns into xx.xxx.010 ?

Is this correct?
Col8 = Col0 & 0x07 | (bias << 3);
Col9 = Col1 & 0x07 | (bias << 3);
...
ColF = Col7 & 0x07 | (bias << 3);

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #173 on: 2022.February.10. 21:54:15 »
Sorry, i used col8-colf, because colours 8-15 are using bias values, and col0-7 use palette value from LPT, if we check 8 colours from bias view only then


Col0   00.000.000  Black
Col1   00.000.001  Dark Red
Col2   00.000.010  Dark Green
Col3   00.000.011  Dark Yellow
Col4   00.000.100  Dark Blue
Col5   00.000.101  Dark Purple
Col6   00.000.110  Dark Cyan
Col7   00.000.111  Dark White


if bias is 00h then the following is the sequence of the bias colours
00h,01h,02h,03h,04h,05h,06h,07h
and because the colour bit setting from bit7-bit0 is grbgrbgr (bias is the bit7-bit3 grbgr and colours are bit2-bit0 bgr) the colors are the following
black,red,green,yellow,blue,purple,cyan,white

Now i checked, your colour assignment uses the speccy method, bit2-0 grb, this mixed the bias colours.
« Last Edit: 2022.February.10. 22:11:36 by geco »

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #174 on: 2022.February.10. 22:25:26 »
Some improvements with interrupts thanks to @Geco explanations :D

28407-0 Now CPU speed is correct

28409-1 Symbos finally works and mouse can be moved with keyboard (or at least starts, I have not tested too much)

I have started some games an timing appears to be good but Bricky does not starts yet.

Offline geco

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #175 on: 2022.February.10. 22:45:36 »
cooool. Bricky uses Dave programmable interrupt for playing the samples, probably it is not implemented.

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #176 on: 2022.February.11. 18:52:56 »
Now CPU speed is correct
Not fully, it is 4.06 instead of 4.00 Mhz :oops:
Also possible because the Nick chip speed are not fully correct.

My CPU speed do INC HL instructions between two video interrupt.
This is the routine:
Code: ZiLOG Z80 Assembler
  1. 0038: JP (IX)
  2. ...
  3.  
  4.                 LD HL,0
  5.                 LD IX,IRQ1
  6.                 LD BC,30B4H
  7.                 OUT (C),B
  8.                 EI
  9.                 HALT
  10. IRQ1            LD IX,IRQ2
  11.                 OUT (C),B
  12.                 EI
  13. IRQW            INC HL
  14.                 JP IRQW
  15. IRQ2            DI
  16.  

Offline Kyp

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #177 on: 2022.February.11. 21:41:40 »
Not fully, it is 4.06 instead of 4.00 Mhz :oops:
Also possible because the Nick chip speed are not fully correct.
Sure, Nick's pixel clock runs at 14,000 MHz, I'll fix that sooner or later :roll:

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #178 on: 2022.February.11. 21:43:37 »
Tonight 22:30 CET

https://www.twitch.tv/retrocrypta

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Re: Enterprise Deployment Attempt Over FPGA.
« Reply #179 on: 2022.February.21. 21:45:09 »
CPU clock: 4.0000 MHz
Pixel clock: 14.2375 MHz

28490-0