Hi there, fellows !
We have some progress, much more than we could expect. Our friend rampa069 has not given us time nor to assimilate all that he has already managed to do. Amazing !
Because the FPGA's SDRAM has 24 addressing bits, rampa069 has successfully reduced the Enterprise MMU in a very smart way. First 8 bits (Content of the port pointed to by the two high lines as a bank) +2 bits (The active port (B0, B1, B2, B3)) + 14 low bits of the address bus..., as soon as a Pseudo_NICK can start painting, there are a lot of possibilities that it will start working right away.
So, Kyp is redoing the control signals but since kyp uses a 28MHz master clock, with clock enables it is more messy. There are a lot of clocks out of combinatorics and that doesn't like the FPGA. The advantage of FPGA implementations is that as milestones are achieved, you can start testing.
Now ROM loads OK, just using a EP128.ROM file at SD's root in where you can concatenate all ROMS you want. It loads from SD at address 0.-
Also the disc controller is working.
Surely tonight ramp069 will enable the Git and all the part already converted to EP128 will be deployed. More or less these are the news we have, it seems that everything is going faster than expected.
Best Regards
ron
