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Author Topic: 6Mhz and more... (Read 19105 times)

Offline pear

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Re: 6Mhz and more...
« Reply #90 on: 2017.September.06. 16:39:44 »
All tools are now complete.
Now "just" the time and I can start.

Online gflorez

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Re: 6Mhz and more...
« Reply #91 on: 2017.September.06. 18:49:34 »
Good looking analyzer. I am tempted, but I don't know how to use it....

Online Zozosoft

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Re: 6Mhz and more...
« Reply #92 on: 2017.September.06. 20:25:41 »
Nice square waves!

Offline pear

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Re: 6Mhz and more...
« Reply #93 on: 2017.September.06. 20:34:08 »
Because it is an analyzer, not an oscilloscope :)
Exactly maps the times of the edge, but the shape of the signal is predetermined.

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Re: 6Mhz and more...
« Reply #94 on: 2017.December.10. 17:34:43 »
Intensive course of the VHDL and the first approach to the turbo generator project.
On board two generators 40 and 48 MHz with CPLD Xillinx XC9572.
Two channel output. Synchronized reset, separated output enablers.
At now not synchronized clocks. Output frequency is switched by 3-bit vectors.
Frequencies:
System channel: 20/16/12/8/4 MHz. CPU clock has system clock with divide by 2.
EXDOS channel: 16/13,33/12/10/9,6/8 MHz.
Code: VHDL
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity turbo is
  7.   port (rst: in  STD_LOGIC;
  8.         enSYS: in std_logic;
  9.         enXDS: in std_logic;
  10.         clk40: in  STD_LOGIC;
  11.         clk48: in  STD_LOGIC;
  12.         selSYS: in  STD_LOGIC_VECTOR (2 downto 0);
  13.         selXDS: in  STD_LOGIC_VECTOR (2 downto 0);
  14.         clkSYS: out  STD_LOGIC;
  15.         clkCPU: out  STD_LOGIC;
  16.         clkXDS: out  STD_LOGIC);
  17. end turbo;
  18.  
  19. architecture Behavioral of turbo is
  20. component div2
  21.   port (clkin : in  STD_LOGIC;
  22.         rst : in  STD_LOGIC;
  23.         clkout : out  STD_LOGIC);
  24. end component;
  25.  
  26. component mod3
  27.   port (clkin: in std_logic;
  28.                           rst: in std_logic;
  29.         clkout: out std_logic);
  30. end component;
  31.  
  32. component mod5
  33.   port (clkin: in std_logic;
  34.                           rst: in std_logic;
  35.         clkout: out std_logic);
  36. end component;
  37.  
  38. component mux8
  39.   port (en: in STD_LOGIC;
  40.         sel: in STD_LOGIC_VECTOR (2 downto 0);
  41.         D0,D1,D2,D3,D4,D5,D6,D7: in STD_LOGIC;
  42.         Q : out STD_LOGIC);
  43. end component;
  44.  
  45. signal clk24: std_logic;
  46. signal clk20: std_logic;
  47. signal clk16: std_logic;
  48. signal clk13: std_logic;
  49. signal clk12: std_logic;
  50. signal clk10: std_logic;
  51. signal clk9: std_logic;
  52. signal clk8: std_logic;
  53. signal clk4: std_logic;
  54. signal clkS: std_logic;
  55.  
  56. begin
  57.   C24: div2 port map (clk48,rst,clk24);
  58.   C20: div2 port map (clk40,rst,clk20);
  59.   C16: mod3 port map (clk48,rst,clk16);
  60.   C13: mod3 port map (clk40,rst,clk13);
  61.   C12: div2 port map (clk24,rst,clk12);
  62.   C10: div2 port map (clk20,rst,clk10);
  63.   C9: mod5 port map (clk48,rst,clk9);
  64.   C8: div2 port map (clk16,rst,clk8);
  65.   C4: div2 port map (clk8,rst,clk4);
  66.   MST: mux8 port map (enSYS,selSYS,clk8,clk12,clk16,clk20,'0','0','0',clk4,clkS);
  67.   MSYS: clkSYS <= clkS;
  68.   MCPU: div2 port map (clkS,rst,clkCPU);
  69.   MXDS: mux8 port map (enXDS,selXDS,clk8,clk9,clk10,clk12,clk13,clk16,'0','0',clkXDS);
  70. end Behavioral;
  71.  

Online gflorez

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Re: 6Mhz and more...
« Reply #95 on: 2017.December.10. 18:32:27 »
It looks good... Needs very few  code to work.

Next you can apply the clocks to the real hardware to see the effect. At first, try to tweak the stock Z80A CPU, Zozo says that some of them can be put up to 7Mhz without problems.

Offline pear

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Re: 6Mhz and more...
« Reply #96 on: 2017.December.10. 18:41:18 »
For now, I used 28 out of 72 macrocells. The synchronization of switching will take a few more.
I hope that there will be enough to the address decoder for RTC and the internal RAM extension.

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Re: 6Mhz and more...
« Reply #97 on: 2017.December.10. 20:25:09 »
Aha! you mean to follow the original plan of adding internal Ram, Rom, RTC and turbo, all at once on a little expansion card...

Offline pear

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Re: 6Mhz and more...
« Reply #98 on: 2017.December.11. 06:22:59 »
Yes :) clocks, RAM and RTC.
I still think about FlashROM. It may be crowded.

Offline pear

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Re: 6Mhz and more...
« Reply #99 on: 2017.December.11. 09:55:50 »
Is there any programm for EP which use a NV RAM inside a RTC chip ?
I could use it for store of Turbo Card configuration.
Then be could control the clocks programmatically straight from the EP.

Online Zozosoft

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Re: 6Mhz and more...
« Reply #100 on: 2017.December.11. 12:01:40 »
Is there any programm for EP which use a NV RAM inside a RTC chip ?
Some bytes used for test presence of RTC chip. (write and read back)

Quote
I could use it for store of Turbo Card configuration.
Then be could control the clocks programmatically straight from the EP.
Good idea!

Offline pear

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Re: 6Mhz and more...
« Reply #101 on: 2017.December.11. 12:06:57 »
Which of them ?
At the start or at the end of those 112 bytes ?

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Re: 6Mhz and more...
« Reply #102 on: 2017.December.12. 21:37:43 »

Offline pear

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Re: 6Mhz and more...
« Reply #103 on: 2017.December.13. 06:22:05 »
Thanks :)

Yesterday I was looking a bit and I was expecting that rather the beginning is checked.
RTC chips have different memory capacities. The last address can be 3Fh or 7Fh.

I also spent a lot of time writing the mod 3 divider in VHDL.
This is not as simple task as it seems.
Especially if the output clock is to be synchronized with the input and the duty cycle should be 50%.
When two conditions are met, the third one is lost.
I have to learn a lot.

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Re: 6Mhz and more...
« Reply #104 on: 2017.December.13. 11:33:54 »
Yesterday I was looking a bit and I was expecting that rather the beginning is checked.
RTC chips have different memory capacities. The last address can be 3Fh or 7Fh.
Yes, I've written about it there.

Just an idea: put the turbo registers to FFh, FEh, etc...
« Last Edit: 2017.December.13. 21:09:19 by szipucsu »