We can use the 7th bit of register no 2 in the CPLD (it is not utilized in the CPLD, but it can be used by the microcontroller) to set whether the clocks should be linked or not.
In the "linked mode", we can stored in the firmware which minimum value of the CLK SYS should be selected for current CLK EXDOS value.
Zozo, can you make for me such a table - value of CLK EXDOS and the corresponding minimum value of CLK SYS ? Please
